Merge branch 'main' into feature/compact-pipeline

sibartel · sibartel · commit 4ee025d52da1 · 2022-02-01T14:01:36.000+01:00
diff --git a/generator/cdc_utils.py b/generator/cdc_utils.py
@@ -22,7 +22,7 @@ def _assign():
 
 
 @block
-def ff_synchronizer(clk, rst, chain_out, chain_in, stages=2, chain_rst_value=0):
+def ff_synchronizer(clk, rst, chain_out, chain_in, stages=3, chain_rst_value=0):
     """
     Flip-Flop based synchronizer. Can be used to stabilize signals which are crossing clock domains.
     Generates a chain with ff_stages flip flops. Use only with 1 bit values if you are not certain
@@ -43,7 +43,7 @@ def ff_synchronizer(clk, rst, chain_out, chain_in, stages=2, chain_rst_value=0):
 
 
 @block
-def areset_synchronizer(clk, async_rst, sync_rst, min_reset_cycles=2):
+def areset_synchronizer(clk, async_rst, sync_rst, min_reset_cycles=3):
     """
     Synchronizer for async reset signals. Uses internally a flip-flop synchronizer.
     :param clk: clock of target domain
diff --git a/generator/generator.py b/generator/generator.py
@@ -262,9 +262,10 @@ def build(*config_files, name=None, config=None):
         2. Invokes :func:`convert` to get generated solver in verilog.
         3. Create build directory for synthesis with OPAE tools.
         4. Preserving solver.v
-        5. Start synthesis and fitting.
-        6. Prepend afu with authentication blocks (with an empty signature chain)
-        7. Create solver file by combining gbs file and solver config.
+        5. Patch build process
+        6. Start synthesis and fitting.
+        7. Prepend afu with authentication blocks (with an empty signature chain)
+        8. Create solver file by combining gbs file and solver config.
     :return:
     """
     if name is None:
@@ -292,9 +293,15 @@ def build(*config_files, name=None, config=None):
     generated_solver_path = os.path.join(generator_path, 'out', 'solver.v')
     shutil.copy(generated_solver_path, build_path)
 
-    # 5. Start synthesis and fitting.
+    # 5. Patch build process
+    clock_crossing_sdc_path = os.path.abspath(os.path.join(generator_path, 'static', 'clock_crossing.sdc'))
+    project_qsf_path = os.path.join(build_path, 'build', 'afu_default.qsf')
+    with open(project_qsf_path, 'a') as project_file:
+        project_file.write(f'\nset_global_assignment -name SDC_FILE "{clock_crossing_sdc_path}"\n')
+
+    # 6. Start synthesis and fitting.
     log_file_path = os.path.join(build_path, 'quartus-run.log')
-    with open(log_file_path, "w") as log_file:
+    with open(log_file_path, 'w') as log_file:
         subprocess.run(
             ['${OPAE_PLATFORM_ROOT}/bin/run.sh'],
             shell=True,
@@ -303,13 +310,13 @@ def build(*config_files, name=None, config=None):
             stderr=subprocess.STDOUT
         ).check_returncode()
 
-    # 6. Prepend afu with authentication blocks (with an empty signature chain)
+    # 7. Prepend afu with authentication blocks (with an empty signature chain)
     subprocess.run(
         ['PACSign PR -t UPDATE -H openssl_manager -y -i solver.gbs -o solver_signed.gbs'],
         shell=True, cwd=build_path
     ).check_returncode()
 
-    # 7. Create solver file by combining gbs file and solver config.
+    # 8. Create solver file by combining gbs file and solver config.
     gbs_path = os.path.join(build_path, 'solver_signed.gbs')
     out_path = os.path.join(os.getcwd(), name)
     if not os.path.isfile(gbs_path):
diff --git a/generator/hram.py b/generator/hram.py
@@ -1,4 +1,4 @@
-from myhdl import block, always_seq, Signal, instances, ConcatSignal, enum, ResetSignal, always_comb
+from myhdl import block, always_seq, Signal, instances, ConcatSignal, enum, always_comb
 
 from framework.data_desc import get_input_desc, get_output_desc
 from framework.packed_struct import BitVector
@@ -17,12 +17,7 @@ def hram_handler(config, cp2af, af2cp, csr: CsrSignals, data_out: AsyncFifoProdu
     assert data_out.clk == data_in.clk
     assert data_out.rst == data_in.rst
     clk = data_out.clk
-
-    reset = ResetSignal(True, True, False)
-
-    @always_comb
-    def reset_driver():
-        reset.next = data_out.rst or not csr.enb
+    reset = data_out.rst
 
     input_desc = get_input_desc(config.system_size)
     assert len(input_desc) <= len(CcipClData)
@@ -56,7 +51,7 @@ def output_finished_driver():
 
     @always_seq(clk.posedge, reset=None)
     def mem_reads_request():
-        if reset:
+        if reset or not csr.enb:
             af2cp.c0.hdr.vc_sel.next = 0
             af2cp.c0.hdr.rsvd1.next = 0
             af2cp.c0.hdr.cl_len.next = 3  # 4 CL's
@@ -99,40 +94,52 @@ def mem_reads_request():
     input_data_size = len(input_desc)
     input_data_iter = Signal(num.UnsignedIntegerNumberType(32).create(0))
 
-    @always_seq(clk.posedge, reset=reset)
+    @always_seq(clk.posedge, reset=None)
     def mem_reads_responses():
-        if data_out.wr:
-            if not data_out.full:
-                nbr_inputs.next = nbr_inputs + 1
-                if input_data_iter + input_data_size <= chunk_size:
-                    data_out.data.next = input_data_chunk[input_data_iter + input_data_size:input_data_iter]
-                    input_data_iter.next = input_data_iter + input_data_size
-                else:
-                    data_out.wr.next = False
-                    input_data_iter.next = 0
-                    cl0_rcv.next = False
-                    cl1_rcv.next = False
-                    cl2_rcv.next = False
-                    cl3_rcv.next = False
-                    read_response_processing_ongoing.next = False
-        elif cl_rcv_vec == 0b1111:
-            data_out.wr.next = True
-            data_out.data.next = input_data_chunk[input_data_iter + input_data_size:input_data_iter]
-            input_data_iter.next = input_data_iter + input_data_size
-            read_response_processing_ongoing.next = True
-        elif cp2af.c0.rspValid == 1 and cp2af.c0.hdr.mdata == 0:
-            if cp2af.c0.hdr.cl_num == 0:
-                cl0_data.next = cp2af.c0.data
-                cl0_rcv.next = True
-            elif cp2af.c0.hdr.cl_num == 1:
-                cl1_data.next = cp2af.c0.data
-                cl1_rcv.next = True
-            elif cp2af.c0.hdr.cl_num == 2:
-                cl2_data.next = cp2af.c0.data
-                cl2_rcv.next = True
-            elif cp2af.c0.hdr.cl_num == 3:
-                cl3_data.next = cp2af.c0.data
-                cl3_rcv.next = True
+        if reset or not csr.enb:
+            nbr_inputs.next = 0
+            input_data_iter.next = 0
+            read_response_processing_ongoing.next = False
+
+            data_out.wr.next = False
+
+            cl0_rcv.next = False
+            cl1_rcv.next = False
+            cl2_rcv.next = False
+            cl3_rcv.next = False
+        else:
+            if data_out.wr:
+                if not data_out.full:
+                    nbr_inputs.next = nbr_inputs + 1
+                    if input_data_iter + input_data_size <= chunk_size:
+                        data_out.data.next = input_data_chunk[input_data_iter + input_data_size:input_data_iter]
+                        input_data_iter.next = input_data_iter + input_data_size
+                    else:
+                        data_out.wr.next = False
+                        input_data_iter.next = 0
+                        cl0_rcv.next = False
+                        cl1_rcv.next = False
+                        cl2_rcv.next = False
+                        cl3_rcv.next = False
+                        read_response_processing_ongoing.next = False
+            elif cl_rcv_vec == 0b1111:
+                data_out.wr.next = True
+                data_out.data.next = input_data_chunk[input_data_iter + input_data_size:input_data_iter]
+                input_data_iter.next = input_data_iter + input_data_size
+                read_response_processing_ongoing.next = True
+            elif cp2af.c0.rspValid == 1 and cp2af.c0.hdr.mdata == 0:
+                if cp2af.c0.hdr.cl_num == 0:
+                    cl0_data.next = cp2af.c0.data
+                    cl0_rcv.next = True
+                elif cp2af.c0.hdr.cl_num == 1:
+                    cl1_data.next = cp2af.c0.data
+                    cl1_rcv.next = True
+                elif cp2af.c0.hdr.cl_num == 2:
+                    cl2_data.next = cp2af.c0.data
+                    cl2_rcv.next = True
+                elif cp2af.c0.hdr.cl_num == 3:
+                    cl3_data.next = cp2af.c0.data
+                    cl3_rcv.next = True
 
     # Incremental counter used for iterating trough host array
     output_addr_offset = Signal(num.UnsignedIntegerNumberType(32).create(0))
@@ -146,7 +153,7 @@ def mem_reads_responses():
 
         @always_seq(clk.posedge, reset=None)
         def reset_padding():
-            if reset:
+            if reset or not csr.enb:
                 output_data_chunk_padding.next = 0
     else:
         output_data_chunk = ConcatSignal(*reversed(output_data))
@@ -157,7 +164,7 @@ def reset_padding():
     # Host Memory Writes
     @always_seq(clk.posedge, reset=None)
     def mem_writes():
-        if reset:
+        if reset or not csr.enb:
             af2cp.c1.hdr.rsvd2.next = 0
             af2cp.c1.hdr.vc_sel.next = 0
             af2cp.c1.hdr.sop.next = 0
diff --git a/generator/static/clock_crossing.sdc b/generator/static/clock_crossing.sdc
@@ -1,5 +1,10 @@
+# Define the clock groups for the clock domain crossing
 set_clock_groups -asynchronous -group [get_clocks "*\|outclk1"] -group [get_clocks "*\|clk1x"]
-set_net_delay -from [get_registers "*\|solver\|rk_interface_x\[*\]"] -to [get_registers "*\|solver\|af2cp_c2_data\[*\]"] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
-set_max_skew -from [get_keepers "*\|solver\|rk_interface_x\[*\]"] -to [get_keepers "*\|solver\|af2cp_c2_data\[*\]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8
-set_net_delay -from [get_registers "*\|solver\|rk_interface_y\[*\]\[*\]"] -to [get_registers "*\|solver\|af2cp_c2_data\[*\]"] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
-set_max_skew -from [get_keepers "*\|solver\|rk_interface_y\[*\]\[*\]"] -to [get_keepers "*\|solver\|af2cp_c2_data\[*\]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8
+
+# Clock domain crossing producer side of all async fifos
+set_net_delay -from [get_registers "*\|solver\|async_fifo*_p_wr_addr_gray\[*\]"] -to [get_registers "*\|solver\|async_fifo*_ff_synchronizer*_out_val\[*\]"] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+set_max_skew -from [get_keepers "*\|solver\|async_fifo*_p_wr_addr_gray\[*\]"] -to [get_keepers "*\|solver\|async_fifo*_ff_synchronizer*_out_val\[*\]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8
+
+# Clock domain crossing consumer side of all async fifos
+set_net_delay -from [get_registers "*\|solver\|async_fifo*_c_rd_addr_gray\[*\]"] -to [get_registers "*\|solver\|async_fifo*_ff_synchronizer*_out_val\[*\]"] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
+set_max_skew -from [get_keepers "*\|solver\|async_fifo*_c_rd_addr_gray\[*\]"] -to [get_keepers "*\|solver\|async_fifo*_ff_synchronizer*_out_val\[*\]"] -get_skew_value_from_clock_period min_clock_period -skew_value_multiplier 0.8
diff --git a/generator/static/filelist.txt b/generator/static/filelist.txt
@@ -9,5 +9,4 @@ ip_cores/subfp_single.ip
 
 ccip_interface_reg.sv
 ccip_std_afu.sv
-../out/solver.v
-clock_crossing.sdc
+../out/solver.v
