Added Acceleration Stack version to README.md.

Author: sibartel

README.md

@@ -5,7 +5,8 @@
 An open source tool that can automatically generate logic circuits from a user-friendly configuration file for efficiently solving systems of ODEs on FPGAs.
 
 ## Supported FPGAs
-Currently, only the *[Intel Programmable Acceleration Card with Intel Arria 10 GX 1150 FPGA](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf)* is supported.
+Currently, only the *[Intel Programmable Acceleration Card with Intel Arria 10 GX 1150 FPGA](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf)*
+using the *Intel Acceleration Stack 1.2.1* is supported.
 If you don't have the required hardware, you can still simulate the logic generated by rtlode (see [Simulation](#simulation)).
 
 ## Installation
@@ -30,16 +31,16 @@ If you want only to simulate the generated logic you can skip step 1, 2 and 3.
 
 2. Create a solver unit with given configuration files:
     ```bash
-    rtlode build heun.yaml predator-prey.yaml
+    rtlode.py build heun.yaml predator-prey.yaml
     ```
 
 3.  To test your solver you can execute the following command:
     ```bash
-    rtlode run heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'
+    rtlode.py run heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'
     ```
     Alternativly a simple benchmark can be performed:
     ```bash
-    rtlode benchmark heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'
+    rtlode.py benchmark heun_predator-prey.slv --runtime_config='{x: 0, y: [0, 2], n: 60, h: 0.17}'
     ```
 
 ## Simulation