fix(abgraph): allowed no matching port preassignment in floorplan config for testing

Author: Ed-5100

bazel/tapa_rules.bzl

@@ -64,6 +64,10 @@ def _tapa_xo_impl(ctx):
     if ctx.file.floorplan_path:
         tapa_cmd.extend(["--floorplan-path", ctx.file.floorplan_path.path])
 
+    # Add floorplan config, if specified.
+    if ctx.file.floorplan_config:
+        tapa_cmd.extend(["--floorplan-config", ctx.file.floorplan_config.path])
+
     # Add device config path, if specified.
     if ctx.file.device_config:
         tapa_cmd.extend(["--device-config", ctx.file.device_config.path])
@@ -114,6 +118,8 @@ def _tapa_xo_impl(ctx):
     inputs = [src] + ctx.files.hdrs + ctx.files.custom_rtl_files
     if ctx.file.floorplan_path:
         inputs.append(ctx.file.floorplan_path)
+    if ctx.file.floorplan_config:
+        inputs.append(ctx.file.floorplan_config)
     if ctx.file.device_config:
         inputs.append(ctx.file.device_config)
     ctx.actions.run(
@@ -169,6 +175,7 @@ tapa_xo = rule(
         "gen_ab_graph": attr.bool(),
         "flatten_hierarchy": attr.bool(),
         "floorplan_path": attr.label(allow_single_file = True),
+        "floorplan_config": attr.label(allow_single_file = True),
         "device_config": attr.label(allow_single_file = True),
         "vitis_hls_env": attr.label(
             cfg = "exec",

tapa/abgraph/gen_abgraph.py

@@ -7,6 +7,7 @@
 """
 
 import json
+import logging
 import re
 from pathlib import Path
 
@@ -20,6 +21,8 @@
 
 MMAP_WIDTH = (405, 43)
 
+_logger = logging.getLogger().getChild(__name__)
+
 
 def get_top_level_ab_graph(program: Program, floorplan_config: Path) -> ABGraph:
     """Generates the top level ab graph."""
@@ -169,7 +172,7 @@ def add_port_iface_connections(  # noqa: C901
 
         if not region:
             msg = f"Port {port.name} does not match any preassignment pattern."
-            raise ValueError(msg)
+            _logger.warning(msg)
 
         dummy_vertex = ABVertex(
             name=port.name,

tapa/steps/floorplan.py

@@ -147,6 +147,8 @@ def get_slot_to_inst(
     return slot_to_insts
 
 
-def convert_region_format(region: str) -> str:
+def convert_region_format(region: str | None) -> str | None:
     """Convert region format from 'x:y' to 'x_TO_y'."""
+    if region is None:
+        return None
     return region.replace(":", "_TO_") if ":" in region else region

tests/functional/abgraph/BUILD.bazel

@@ -15,6 +15,7 @@ tapa_xo(
     include = ["."],
     enable_synth_util = True,
     flatten_hierarchy = True,
+    floorplan_config = ":test_fp_config.json",
     gen_ab_graph = True,
     top_name = "VecAdd",
 )
@@ -45,6 +46,7 @@ tapa_xo(
     include = ["."],
     enable_synth_util = True,
     flatten_hierarchy = True,
+    floorplan_config = ":test_fp_config.json",
     gen_ab_graph = True,
     top_name = "Bandwidth",
 )
@@ -74,6 +76,7 @@ tapa_xo(
     include = ["."],
     enable_synth_util = True,
     flatten_hierarchy = True,
+    floorplan_config = ":test_fp_config.json",
     gen_ab_graph = True,
     top_name = "Cannon",
 )
@@ -103,6 +106,7 @@ tapa_xo(
     include = ["."],
     enable_synth_util = True,
     flatten_hierarchy = True,
+    floorplan_config = ":test_fp_config.json",
     gen_ab_graph = True,
     top_name = "Network",
 )

tests/functional/abgraph/test_fp_config.json

@@ -0,0 +1,20 @@
+{
+    "cell_pre_assignments": {},
+    "cpp_arg_pre_assignments": {},
+    "dse_range_max": 0.8,
+    "dse_range_min": 0.65,
+    "grouping_constraints": [],
+    "ignore_narrow_edge_threshold": 1,
+    "max_seconds": 600,
+    "partition_schedule": [],
+    "partition_strategy": "flat",
+    "reserved_slot_to_cells": {},
+    "slot_to_rtype_to_max_limit": {},
+    "slot_to_rtype_to_min_limit": {},
+    "sys_port_pre_assignments": {
+        "ap_clk": "SLOT_X2Y0:SLOT_X2Y0",
+        "ap_rst_n": "SLOT_X2Y0:SLOT_X2Y0",
+        "interrupt": "SLOT_X2Y0:SLOT_X2Y0",
+        "s_axi_control_.*": "SLOT_X2Y1:SLOT_X2Y1"
+    }
+}