more docs updates

Author: timsherwood

docs/analysis.rst

@@ -5,16 +5,17 @@
 .. _top-of-page-analysis:
 
 
-========
-Analysis
-========
+=========================
+Analysis and Optimization
+=========================
 
-Provides tools for analyzing aspects of PyRTL designs
+Provides tools for analyzing ad optimizing aspects of PyRTL designs
 
+Estimation
+----------
 
 .. | :ref:`estimate-ref`
 
-
 .. .. _estimate-ref:
 
 .. automodule:: pyrtl.analysis.estimate
@@ -24,5 +25,26 @@ Provides tools for analyzing aspects of PyRTL designs
    :undoc-members:
    :exclude-members: __dict__,__weakref__,__module__
 
-:ref:`Back to top of page <top-of-page-analysis>`
+Optimization
+------------
+
+.. autofunction:: pyrtl.passes.optimize
+
+Synthesis
+---------
+
+.. autofunction:: pyrtl.passes.synthesize
 
+.. autoclass:: pyrtl.core.PostSynthBlock
+
+Individual Passes
+-----------------
+
+.. autofunction:: pyrtl.passes.common_subexp_elimination
+.. autofunction:: pyrtl.passes.constant_propagation
+.. autofunction:: pyrtl.passes.nand_synth
+.. autofunction:: pyrtl.passes.and_inverter_synth
+.. autofunction:: pyrtl.passes.one_bit_selects
+.. autofunction:: pyrtl.passes.two_way_concat
+
+:ref:`Back to top of page <top-of-page-analysis>`

docs/index.rst

@@ -140,45 +140,6 @@ PyrtlInternalError captures internal invariants and assertions over the core log
 be hit when constructing designs in the normal ways.  If you hit a confusing `PyrtlError` or any
 `PyrtlInternalError` feel free to file an issue.
 
-PyRTL Quick Reference:
-----------------------
-
-* Helpful RTL constructs
-    * mux(index_val, val_1, val_2, ... val_n, default=val_x)
-    * select(selector, truecase, falsecase)
-    * concat(wire_msbs, wire_next, ..., wire_lsbs) 
-    * concat_list(wire_list)  # wire_list[0] will be lsb
-    * barrel_shifter(shift_in, bit_in, direction, shift_dist, wrap_around=0)
-    * prioritized_mux(select_list, val_list)  # priority encoder
-    * sparse_mux(selects, vals)
-    * mult_signed(val1, val2)
-
-* Functions useful for test and debug:
-    * set_debug_mode(debug=True)
-    * probe(wire, name=None)
-    * rtl_assert(test_wire, exception_to_be_thrown, block=None)
-    * working_block(block=None)
-    * reset_working_block()
-    * twos_comp_repr(val, bitwidth)
-    * rev_twos_comp_repr(val, bitwidth)
-
-* Allocating and modifying wirevectors
-    * as_wires(val, bitwidth=None, truncating=True, block=None)
-    * match_bitwidth(a, b, c, ..., signed=False)
-    * partition_wire(wire, partition_size)
-    * input_list(names, bitwidth=1)
-    * output_list(names, bitwidth=1)
-    * register_list(names, bitwidth=1)
-    * wirevector_list(names, bitwidth=1, wvtype=WireVector)
-    * WireVector.sign_extended(bitwidth)
-    * WireVector.zero_extended(bitwidth)
-
-* Estimating and optimizing hardware
-    * timing_estimation(tech_in_nm=130, block=None)
-    * area_estimation(tech_in_nm=130, block=None)
-    * yosys_area_delay(library, abc_cmd=None, block=None)
-    * optimize(update_working_block=True, block=None)
-    * synthesize(update_working_block=True, block=None)
 
 PyRTL Functionality:
 ====================
@@ -193,7 +154,6 @@ PyRTL Functionality:
    analysis
    export
    rtllib
-   advanced
 
 
 Indices and tables