more docs

Author: timsherwood

docs/helpers.rst

@@ -19,4 +19,3 @@ Hardware Design Helper Functions
    :special-members:
    :undoc-members:
    :exclude-members: __dict__,__weakref__,__module__
-

pyrtl/wire.py

@@ -107,6 +107,13 @@ def __init__(self, bitwidth=None, name='', block=None):
         :param String name: The name of the wire referred to in some places.
          Must be unique. If none is provided, one will be autogenerated
         :return: a wirevector object representing a const wire
+
+        Examples::
+
+            data = pyrtl.WireVector(8, 'data')  # visible in trace as "data"
+            ctrl = pyrtl.WireVector(1)  # assigned tmp name, not visible in traces by default
+            temp = pyrtl.WireVector()  # temporary with width to be defined later
+            temp <<= data  # this this case temp will get the bitwdith of 8 from data
         """
         self._name = None
 
@@ -170,7 +177,14 @@ def _prepare_for_assignment(self, rhs):
         return rhs
 
     def __ilshift__(self, other):
-        """ Wire assignment operator (assign other to self). """
+        """ Wire assignment operator (assign other to self).
+
+        Example::
+
+            i = pyrtl.Input(8, 'i')
+            t = pyrtl.WireVector(8, 't')
+            t <<= i
+        """
         other = self._prepare_for_assignment(other)
         self._build(other)
         return self
@@ -228,6 +242,10 @@ def __bool__(self):
     def __and__(self, other):
         """ Creates a LogicNet that ands two wires together into a single wire
             :return Wirevector: the result wire of the operation
+
+            Example::
+
+                temp = a & b
         """
         return self._two_var_op(other, '&')
 
@@ -240,6 +258,10 @@ def __iand__(self, other):
     def __or__(self, other):
         """ Creates a LogicNet that ors two wires together into a single wire
             :return Wirevector: the result wire of the operation
+
+            Example::
+
+                temp = a | b
         """
         return self._two_var_op(other, '|')
 
@@ -267,6 +289,13 @@ def __add__(self, other):
           The resulting wire has one more bit than the longer of the two input wires.
 
         Addition is compatible with two's complement signed numbers.
+
+        Examples::
+
+            temp = a + b  # simple addition of two wirevectors
+            temp = a + 5  # you can use integers
+            temp = a + 0b110  # you can use other integers
+            temp = a + "3'h7"  # compatable verilog constants work too
         """
         return self._two_var_op(other, '+')
 
@@ -517,7 +546,7 @@ def _extend_with_bit(self, bitwidth, extbit):
 #
 
 class Input(WireVector):
-    """ A WireVector type denoting inputs to a block (no writers) """
+    """ A WireVector type denoting inputs to a block (no writers)."""
     _code = 'I'
 
     def __init__(self, bitwidth=None, name='', block=None):