Keep user-defined const name after synthesis; error in simulation if only named wires are consts

Author: mdko

pyrtl/passes.py

@@ -408,7 +408,7 @@ def synthesize(update_working_block=True, block=None):
                 new_name = '_'.join((wirevector.name, 'synth', str(i)))
                 if isinstance(wirevector, Const):
                     new_val = (wirevector.val >> i) & 0x1
-                    new_wirevector = Const(bitwidth=1, val=new_val)
+                    new_wirevector = Const(name=new_name, bitwidth=1, val=new_val)
                 elif isinstance(wirevector, (Input, Output)):
                     new_wirevector = WireVector(name="tmp_" + new_name, bitwidth=1)
                 else:

pyrtl/simulation.py

@@ -1001,8 +1001,9 @@ def is_internal_name(name):
         elif wires_to_track == 'all':
             wires_to_track = self.block.wirevector_set
 
-        if not len(wires_to_track):
-            raise PyrtlError("There needs to be at least one named wire "
+        non_const_tracked = list(filter(lambda w: not isinstance(w, Const), wires_to_track))
+        if not len(non_const_tracked):
+            raise PyrtlError("There needs to be at least one named non-constant wire "
                              "for simulation to be useful")
         self.wires_to_track = wires_to_track
         self.trace = TraceStorage(wires_to_track)