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Rhys Gretsch
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Implement a language agnostic hardware representation
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‎pyrtl/hardwareSchema.py‎

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def hardwareSchema():
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''' This function holds the schemas to check that any json hardware
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representation conforms to the same requirements
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All components except for inputs should have some driving logic
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If the driving logic does not list an operation it is a simple
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assignment operation (destination = argument)
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Arguments should always be listed from left to right as one might
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read them in a language like verilog
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EX. a + b becomes op='+', args=[a,b]
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Ex. a ? b : c becomes op='?', args=[a, b, c]
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Ex. {a, b} becomes op='concat', args=[a,b]
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If the module does not have a primary component (inputs, outputs,
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registers, wires, memory) their field should be included with an
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empty list
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'''
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nameSchema = {
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"description": "The component's name",
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"type": "string"
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}
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bitwidthSchema = {
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"description": "The number of bits this component contains",
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"type": "integer"
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}
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componentSchema = {
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"name": nameSchema,
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"bitwidth": bitwidthSchema,
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"Constant value": {
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"description": "If this is a constant this field holds its constant value",
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"type": "integer"
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},
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"driver": {
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"description": "The operation or wire that drives this component",
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"type": "object",
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"properties": {
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"op": {
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"description": "Logical operation whose output is driving this component",
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"type": "string"
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},
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"args": {
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"description": """A list of the arguments of the operation,
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in order of left to right""",
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"type": "array",
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"items": {
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"description": "Individual arguments",
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"type": "string"
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}
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},
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"src": {
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"description": "The component input into a register",
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"type": "string"
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},
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"rst val": {
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"description": "If this is a register, this lists what it should be reset to",
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"type": "integer"
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}
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}
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}
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}
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memorySchema = {
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"name": nameSchema,
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"bitwidth": bitwidthSchema,
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"size": {
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"description": "The number of addressable locations",
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"type": "integer"
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},
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"initial values": {
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"description": "For ROM memory this outlines each address' initial value as an integer",
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"type": "array",
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"items": {
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"description": """The index in the list is the memory address each
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intial value maps to""",
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"type": "integer"
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}
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},
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"reads": {
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"description": "A list of all read operations ocurring on this memory",
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"type": "array",
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"items": {
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"description": "A single memory read operation",
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"type": "object",
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"properties": {
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"destination": {
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"description": "The component receiving the result of the read operation",
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"type": "string"
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},
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"addr": {
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"description": "The wire name that selects the memory address to be read",
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"type": "string"
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}
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},
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"required": ["destination", "addr"]
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}
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},
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"writes": {
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"description": "A list of all the write operations to this memory",
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"type": "array",
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"items": {
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"description": "A single memory write operation",
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"type": "object",
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"properties": {
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"addr": {
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"description": """The component that selects the
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memory address to be written""",
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"type": "string"
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},
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"data src": {
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"description": """The component that provides the
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data to be written to memory""",
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"type": "string"
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},
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"w.e": {
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"description": "The component that controls the write enable if applicable",
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"type": "string"
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},
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},
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"required": ["addr", "data src"]
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}
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}
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}
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exportSchema = {
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# necessary for version control
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"$schema": "https://json-schema.org/draft/2020-12/schema",
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"title": "JSON Hardware representation",
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"type": "object",
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"properties": {
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"module": {
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"description": "The top level module",
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"type": "object",
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"properties": {
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"name": {
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"description": "The module name",
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"type": "string"
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},
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"inputs": {
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"description": "List of inputs to the module",
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"type:": "array",
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"items": {
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"description": "An input into the module",
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"type": "object",
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"properties": componentSchema,
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"required": ["name", "bitwidth"]
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},
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"uniqueItems": True
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},
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"outputs": {
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"description": "List of the module's outputs",
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"type": "array",
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"items": {
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"description": "An output of the module",
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"type": "object",
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"properties": componentSchema,
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"required": ["name", "bitwidth", "driver"]
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},
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"uniqueItems": True
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},
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"wires": {
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"description": "List of the internal wires in the module",
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"type": "array",
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"items": {
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"description": "A wire in the module",
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"type": "object",
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"properties": componentSchema,
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"required": ["name", "bitwidth"]
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},
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"uniqueItems": True
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},
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"registers": {
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"description": "List of the internal registers in the module",
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"type": "array",
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"items": {
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"description": "A register in the module",
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"type": "object",
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"properties": componentSchema,
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"required": ["name", "bitwidth", "driver"]
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},
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"uniqueItems": True
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},
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"memories": {
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"description": "List of memories and their respective accesses",
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"type": "array",
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"items": {
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"description": "A single memory module",
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"type": "object",
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"properties": memorySchema,
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"required": ['name', 'bitwidth', 'size']
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},
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"uniqueItems": True
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},
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},
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"required": ["name", "inputs", "outputs",
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"wires", "registers", "memories"]
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}
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}
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}
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return exportSchema

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