Don't generate nands on BLIF import

Author: mdko

pyrtl/importexport.py

@@ -325,17 +325,21 @@ def twire(w):
             output_wire = twire(netio[2])
             output_wire <<= twire(netio[0]) | twire(netio[1])  # or gate
         elif command['cover_list'].asList() == ['0-', '1', '-0', '1']:
+            # nand is not really a PyRTL primitive and so should only be added to a netlist
+            # via a call to nand_synth(). We instead convert it to ~(a & b) rather than
+            # (~a | ~b) as would be generated if handled by the else case below.
             output_wire = twire(netio[2])
-            output_wire <<= twire(netio[0]).nand(twire(netio[1]))  # nand gate
+            output_wire <<= ~(twire(netio[0]) & twire(netio[1]))  # nand gate -> not+and gates
         elif command['cover_list'].asList() == ['10', '1', '01', '1']:
             output_wire = twire(netio[2])
             output_wire <<= twire(netio[0]) ^ twire(netio[1])  # xor gate
         else:
             # Although the following is fully generic and thus encompasses all of the
             # special cases after the simple wire case above, we leave the above in because
             # they are commonly found and lead to a slightly cleaner (though equivalent) netlist,
-            # because we can use nand/xor primitives, or avoid the extra fluff of concat/select
-            # wires that might be created implicitly as part of rtl_all/rtl_any.
+            # because we can use the xor primitive/save a gate when converting the nand, or avoid
+            # the extra fluff of concat/select wires that might be created implicitly as part of
+            # rtl_all/rtl_any.
             def convert_val(ix, val):
                 wire = twire(netio[ix])
                 if val == '0':

tests/test_importexport.py

@@ -663,7 +663,9 @@ def test_blif_or_gate_correct(self):
         })
         self.assertEqual(sim.tracer.trace['o'], [0, 1, 1, 1])
 
-    def test_blif_nand_gate_correct(self):
+    def test_blif_nand_gate_to_primitives_correct(self):
+        # This tests that there should be no NAND gates generated during BLIF import;
+        # they should be converted to AND+NOT.
         blif = """\
         .model Top
         .inputs a b
@@ -675,7 +677,9 @@ def test_blif_nand_gate_correct(self):
         """
         pyrtl.input_from_blif(blif)
         block = pyrtl.working_block()
-        self.assertEqual(len(block.logic_subset('n')), 1)
+        self.assertEqual(len(block.logic_subset('n')), 0)
+        self.assertEqual(len(block.logic_subset('&')), 1)
+        self.assertEqual(len(block.logic_subset('~')), 1)
         sim = pyrtl.Simulation()
         sim.step_multiple({
             'a': '0011',