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1 parent 1e9ad79 commit 756d6c1Copy full SHA for 756d6c1
tests/test_importexport.py
@@ -1650,7 +1650,7 @@ class TestVerilogInput(unittest.TestCase):
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def setUp(self):
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import subprocess
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try:
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- version = subprocess.check_output(['yosys', '--version'])
+ version = subprocess.check_output(['yosys', '-V'])
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except OSError:
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raise unittest.SkipTest('Testing Verilog input requires yosys')
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pyrtl.reset_working_block()
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