Cleanup tests by removing deprecated unittest methods, trace access by wire

mdko · mdko · commit 86832fef3437 · 2021-06-10T00:49:56.000-07:00
diff --git a/pyrtl/helperfuncs.py b/pyrtl/helperfuncs.py
@@ -815,7 +815,7 @@ def dead_end():
 
     # now making a map to quickly look up nets
     dest_nets = {dest_w: net_ for net_ in logic_left for dest_w in net_.dests}
-    initial_w = random.sample(wires_left, 1)[0]
+    initial_w = random.sample(list(wires_left), 1)[0]
 
     current_wires = set()
     checking_stack = [_FilteringState(initial_w)]
diff --git a/pyrtl/importexport.py b/pyrtl/importexport.py
@@ -772,7 +772,7 @@ def default_value():
                 print('        {:s} = {:s}{:d};'.format(
                     ver_name[w.name],
                     "{:d}'d".format(len(w)),
-                    simulation_trace.trace[w][i]), file=dest_file)
+                    simulation_trace.trace[w.name][i]), file=dest_file)
             if cmd:
                 print('        %s' % cmd, file=dest_file)
             print('\n        #10', file=dest_file)
diff --git a/pyrtl/rtllib/testingutils.py b/pyrtl/rtllib/testingutils.py
@@ -89,7 +89,7 @@ def sim_and_ret_out(outwire, inwires, invals):
     :return: a list of values from the output wire simulation result
     """
     # Pulling the value of outwire straight from the log
-    return sim_and_ret_outws(inwires, invals)[outwire]
+    return sim_and_ret_outws(inwires, invals)[outwire.name]
 
 
 def sim_and_ret_outws(inwires, invals):
diff --git a/pyrtl/simulation.py b/pyrtl/simulation.py
@@ -1025,15 +1025,15 @@ def add_step(self, value_map):
             raise PyrtlError('error, simulation trace needs at least 1 signal to track '
                              '(by default, unnamed signals are not traced -- try either passing '
                              'a name to a WireVector or setting a "wirevector_subset" option)')
-        for wire in self.trace:
-            tracelist = self.trace[wire]
-            wirevec = self._wires[wire]
+        for wire_name in self.trace:
+            tracelist = self.trace[wire_name]
+            wirevec = self._wires[wire_name]
             tracelist.append(value_map[wirevec])
 
     def add_step_named(self, value_map):
-        for wire in value_map:
-            if wire in self.trace:
-                self.trace[wire].append(value_map[wire])
+        for wire_name in value_map:
+            if wire_name in self.trace:
+                self.trace[wire_name].append(value_map[wire_name])
 
     def add_fast_step(self, fastsim):
         """ Add the fastsim context to the trace. """
diff --git a/tests/rtllib/test_aes.py b/tests/rtllib/test_aes.py
@@ -206,7 +206,7 @@ def test_aes_state_machine(self):
                 self.in_vector: 0x0, aes_key: 0x1, reset: 0
             })
             circuit_out = sim_trace.trace[self.out_vector][cycle]
-            sim_trace.render_trace(symbol_len=40)
+            # sim_trace.render_trace(symbol_len=40)
             self.assertEqual(circuit_out, true_vals[cycle], "\nAssertion failed on cycle: "
                              + str(cycle) + " Gotten value: " + hex(circuit_out))
 
diff --git a/tests/rtllib/test_barrel.py b/tests/rtllib/test_barrel.py
@@ -34,8 +34,8 @@ def test_shift_left(self):
                 self.inp_shift: shifts[i]
             })
             base_sum = vals[i] * pow(2, shifts[i])
-            self.assertEquals(sim.inspect(self.out_zeros), base_sum)
-            self.assertEquals(sim.inspect(self.out_ones), base_sum + pow(2, shifts[i]) - 1)
+            self.assertEqual(sim.inspect(self.out_zeros), base_sum)
+            self.assertEqual(sim.inspect(self.out_ones), base_sum + pow(2, shifts[i]) - 1)
 
     def test_shift_right(self):
         random.seed(777906374)
@@ -55,5 +55,5 @@ def test_shift_right(self):
             base_sum = int(vals[i] / pow(2, shifts[i]))
             self.assertEqual(sim.inspect(self.out_zeros), base_sum, "failed on value %d" % vals[i])
             extra_sum = sum([pow(2, len(self.inp_val) - b - 1) for b in range(shifts[i])])
-            self.assertEquals(sim.inspect(self.out_ones), base_sum + extra_sum,
-                              "failed on value %d" % vals[i])
+            self.assertEqual(sim.inspect(self.out_ones), base_sum + extra_sum,
+                             "failed on value %d" % vals[i])
diff --git a/tests/rtllib/test_libutils.py b/tests/rtllib/test_libutils.py
@@ -31,7 +31,7 @@ def test_partition_sim(self):
         partitioned_vals = [[(val >> i) & 0xff for i in (0, 8, 16, 24)] for val in vals[0]]
         true_vals = tuple(zip(*partitioned_vals))
         for index, wire in enumerate(out_wires):
-            self.assertEqual(tuple(out_vals[wire]), true_vals[index])
+            self.assertEqual(tuple(out_vals[wire.name]), true_vals[index])
 
 
 class TestStringConversion(unittest.TestCase):
@@ -76,7 +76,7 @@ def setUp(self):
 
     def test_inverse_functionality(self):
         for i in range(20):
-            self.assertEquals(i * 3, libutils.rev_twos_comp_repr(
+            self.assertEqual(i * 3, libutils.rev_twos_comp_repr(
                 libutils.twos_comp_repr(i * 3, 16), 16))
 
     def test_low_bw_error(self):
@@ -96,4 +96,4 @@ def test_twos_comp_sim(self):
                 'in1': i,
                 'in2': libutils.twos_comp_repr(-2 * i, 8)
             })
-            self.assertEquals(-i, libutils.rev_twos_comp_repr(sim.inspect('out'), 8))
+            self.assertEqual(-i, libutils.rev_twos_comp_repr(sim.inspect('out'), 8))
diff --git a/tests/rtllib/test_matrix.py b/tests/rtllib/test_matrix.py
@@ -2450,20 +2450,20 @@ def setUp(self):
         pyrtl.reset_working_block()
 
     def test_list_to_int(self):
-        self.assertEquals(Matrix.list_to_int([[0]], 1), 0b0)
-        self.assertEquals(Matrix.list_to_int([[1, 2]], 2), 0b0110)
-        self.assertEquals(Matrix.list_to_int([[1, 2, 3]], 2), 0b011011)
-        self.assertEquals(Matrix.list_to_int([[4, 9, 11], [3, 5, 6]], 4),
-                          0b010010011011001101010110)
+        self.assertEqual(Matrix.list_to_int([[0]], 1), 0b0)
+        self.assertEqual(Matrix.list_to_int([[1, 2]], 2), 0b0110)
+        self.assertEqual(Matrix.list_to_int([[1, 2, 3]], 2), 0b011011)
+        self.assertEqual(Matrix.list_to_int([[4, 9, 11], [3, 5, 6]], 4),
+                         0b010010011011001101010110)
 
     def test_list_to_int_truncates(self):
-        self.assertEquals(Matrix.list_to_int([[4, 9, 27]], 3), 0b100001011)
+        self.assertEqual(Matrix.list_to_int([[4, 9, 27]], 3), 0b100001011)
 
     def test_list_to_int_negative(self):
-        self.assertEquals(Matrix.list_to_int([[-4, -9, 11]], 5), 0b111001011101011)
+        self.assertEqual(Matrix.list_to_int([[-4, -9, 11]], 5), 0b111001011101011)
 
     def test_list_to_int_negative_truncates(self):
-        self.assertEquals(Matrix.list_to_int([[-4, -9, 11]], 3), 0b100111011)
+        self.assertEqual(Matrix.list_to_int([[-4, -9, 11]], 3), 0b100111011)
 
     def test_list_to_int_non_positive_n_bits(self):
         with self.assertRaises(pyrtl.PyrtlError):
diff --git a/tests/rtllib/test_multipliers.py b/tests/rtllib/test_multipliers.py
@@ -32,7 +32,7 @@ def mult_t_base(self, len_a, len_b):
         m_prod, m_done = multipliers.simple_mult(a, b, reset)
         product <<= m_prod
         done <<= m_done
-        self.assertEquals(len(product), len_a + len_b)
+        self.assertEqual(len(product), len_a + len_b)
 
         xvals = [int(random.uniform(0, 2 ** len_a - 1)) for i in range(20)]
         yvals = [int(random.uniform(0, 2 ** len_b - 1)) for i in range(20)]
@@ -89,7 +89,7 @@ def mult_t_base(self, len_a, len_b, shifts):
         m_prod, m_done = multipliers.complex_mult(a, b, shifts, reset)
         product <<= m_prod
         done <<= m_done
-        self.assertEquals(len(product), len_a + len_b)
+        self.assertEqual(len(product), len_a + len_b)
 
         xvals = [int(random.uniform(0, 2 ** len_a - 1)) for i in range(20)]
         yvals = [int(random.uniform(0, 2 ** len_b - 1)) for i in range(20)]
@@ -129,7 +129,7 @@ def mult_t_base(self, len_a, len_b, **mult_args):
         product = pyrtl.Output(name="product")
         product <<= multipliers.tree_multiplier(a, b, **mult_args)
 
-        self.assertEquals(len(product), len_a + len_b)
+        self.assertEqual(len(product), len_a + len_b)
 
         # creating the testing values and the correct results
         xvals = [int(random.uniform(0, 2 ** len_a - 1)) for i in range(20)]
@@ -143,7 +143,7 @@ def mult_t_base(self, len_a, len_b, **mult_args):
             sim.step({a: xvals[cycle], b: yvals[cycle]})
 
         # Extracting the values and verifying correctness
-        multiplier_result = sim_trace.trace[product]
+        multiplier_result = sim_trace.trace[product.name]
         self.assertEqual(multiplier_result, true_result)
 
     def test_trivial_case(self):
@@ -211,7 +211,7 @@ def mult_t_base(self, len_a, len_b, **mult_args):
         product = pyrtl.Output(name="product")
         product <<= multipliers.signed_tree_multiplier(a, b, **mult_args)
 
-        self.assertEquals(len(product), len_a + len_b)
+        self.assertEqual(len(product), len_a + len_b)
 
         # creating the testing values and the correct results
         bound_a = 2 ** (len_a - 1) - 1
@@ -231,7 +231,7 @@ def mult_t_base(self, len_a, len_b, **mult_args):
 
         # Extracting the values and verifying correctness
         multiplier_result = [libutils.rev_twos_comp_repr(p, len(product))
-                             for p in sim_trace.trace[product]]
+                             for p in sim_trace.trace[product.name]]
         self.assertEqual(multiplier_result, true_result)
 
     def test_small_bitwidth_error(self):
diff --git a/tests/rtllib/test_muxes.py b/tests/rtllib/test_muxes.py
@@ -274,8 +274,8 @@ def test_really_simple(self):
         expected_i1_out = [v1 if s else v0 for s, v0, v1 in zip(sel_vals, i1_0_vals, i1_1_vals)]
         expected_i2_out = [v1 if s else v0 for s, v0, v1 in zip(sel_vals, i2_0_vals, i2_1_vals)]
 
-        self.assertEqual(actual_outputs[i1_out], expected_i1_out)
-        self.assertEqual(actual_outputs[i2_out], expected_i2_out)
+        self.assertEqual(actual_outputs[i1_out.name], expected_i1_out)
+        self.assertEqual(actual_outputs[i2_out.name], expected_i2_out)
 
     def test_simple(self):
         sel, sel_vals = gen_in(2)
@@ -300,9 +300,9 @@ def test_simple(self):
         expected_i2_out = [v[s] for s, v in zip(sel_vals, zip(*x2_vals))]
         expected_i3_out = [v[s] for s, v in zip(sel_vals, zip(*x3_vals))]
 
-        self.assertEqual(actual_outputs[i1_out], expected_i1_out)
-        self.assertEqual(actual_outputs[i2_out], expected_i2_out)
-        self.assertEqual(actual_outputs[i3_out], expected_i3_out)
+        self.assertEqual(actual_outputs[i1_out.name], expected_i1_out)
+        self.assertEqual(actual_outputs[i2_out.name], expected_i2_out)
+        self.assertEqual(actual_outputs[i3_out.name], expected_i3_out)
 
 
 class TestDemux(unittest.TestCase):
diff --git a/tests/test_analysis.py b/tests/test_analysis.py
@@ -37,7 +37,7 @@ def test_area_est_unchanged(self):
         atimesb <<= a * b
         memread <<= mem[0]
         mem[1] <<= a
-        self.assertEquals(pyrtl.area_estimation(), (0.00734386752, 0.01879779717361501))
+        self.assertEqual(pyrtl.area_estimation(), (0.00734386752, 0.01879779717361501))
 
     def test_area_est_unchanged_with_rom(self):
         a = pyrtl.Const(2, 8)
@@ -66,7 +66,7 @@ def test_area_est_unchanged_with_rom(self):
         bminusa <<= a - b
         atimesb <<= a * b
         memread <<= mem[reg]
-        self.assertEquals(pyrtl.area_estimation(), (0.00734386752, 0.001879779717361501))
+        self.assertEqual(pyrtl.area_estimation(), (0.00734386752, 0.001879779717361501))
 
 
 class TestTimingEstimate(unittest.TestCase):
@@ -104,7 +104,7 @@ def test_time_est_unchanged(self):
         mem[1] <<= a
         timing = pyrtl.TimingAnalysis()
         self.assertEqual(timing.max_freq(), 610.2770657878676)
-        self.assertEquals(timing.max_length(), 1255.6000000000001)
+        self.assertEqual(timing.max_length(), 1255.6000000000001)
 
 
 class TestYosysInterface(unittest.TestCase):
diff --git a/tests/test_compilesim.py b/tests/test_compilesim.py
@@ -734,7 +734,7 @@ def test_mem_val_map(self):
                 self.write_data: 2 + i
             })
         # check consistency of memory_value_map assignment, insertion, and modification
-        self.assertEquals(sim.inspect_mem(self.mem1), {0: 0, 1: 2, 2: 3, 3: 3, 4: 4, 5: 5})
+        self.assertEqual(sim.inspect_mem(self.mem1), {0: 0, 1: 2, 2: 3, 3: 3, 4: 4, 5: 5})
 
     def test_mem_val_map_defaults(self):
         read_addr3 = pyrtl.Input(self.addrwidth)
@@ -1012,7 +1012,7 @@ def test_empty_trace_after_untraceable_removed(self):
         sim.step_multiple(provided_inputs={}, nsteps=10)
         with self.assertRaises(pyrtl.PyrtlError) as ex:
             sim.tracer.render_trace()
-        self.assertEquals(
+        self.assertEqual(
             str(ex.exception),
             "Empty trace list. This may have occurred because "
             "untraceable wires were removed prior to simulation, "
diff --git a/tests/test_conditional.py b/tests/test_conditional.py
@@ -525,7 +525,7 @@ def test_super_stress_test(self):
             t0, t1, t2, t3, t4 = 0, 0, 0, 0, 0
 
             def v(var):
-                return sim_trace.trace[var][cycle]
+                return sim_trace.trace[var.name][cycle]
 
             if v(a):
                 t0 = 1
diff --git a/tests/test_core.py b/tests/test_core.py
@@ -122,7 +122,7 @@ def tearDown(self):
         pyrtl.reset_working_block()
 
     def invalid_net(self, exp_message, *args):
-        with self.assertRaisesRegexp(pyrtl.PyrtlInternalError, exp_message):
+        with self.assertRaisesRegex(pyrtl.PyrtlInternalError, exp_message):
             pyrtl.working_block().add_net(*args)
 
     @staticmethod
@@ -477,7 +477,7 @@ def setUp(self):
         pyrtl.reset_working_block()
 
     def sanity_error(self, msg, error_type=pyrtl.PyrtlError):
-        with self.assertRaisesRegexp(error_type, msg):
+        with self.assertRaisesRegex(error_type, msg):
             pyrtl.working_block().sanity_check()
 
     def test_missing_bitwidth(self):
diff --git a/tests/test_helperfuncs.py b/tests/test_helperfuncs.py
@@ -1018,7 +1018,7 @@ def mult_t_base(self, len_a, len_b):
             sim.step({a: xvals[cycle], b: yvals[cycle]})
 
         # Extracting the values and verifying correctness
-        multiplier_result = sim_trace.trace[product]
+        multiplier_result = sim_trace.trace[product.name]
         self.assertEqual(multiplier_result, true_result)
 
     def test_mult_1(self):
diff --git a/tests/test_importexport.py b/tests/test_importexport.py
diff --git a/tests/test_memblock.py b/tests/test_memblock.py
diff --git a/tests/test_simulation.py b/tests/test_simulation.py
diff --git a/tests/test_transform.py b/tests/test_transform.py
