Add option to emit 1-bit io after synthesis, and track io_map in

PostSynth block.

Author: mdko

pyrtl/passes.py

@@ -5,6 +5,7 @@
 """
 
 from __future__ import print_function, unicode_literals
+from re import I
 
 from .core import working_block, set_working_block, _get_debug_mode, LogicNet, PostSynthBlock
 from .helperfuncs import _NetCount
@@ -351,11 +352,14 @@ def _remove_unused_wires(block, keep_inputs=True):
 #
 
 
-def synthesize(update_working_block=True, block=None):
+def synthesize(update_working_block=True, merge_io_vectors=True, block=None):
     """ Lower the design to just single-bit "and", "or", "xor", and "not" gates.
 
-    :param update_working_block: Boolean specifying if working block update
-    :param block: The block you want to synthesize
+    :param update_working_block: Boolean specifying if working block should
+        be set to the newly synthesized block.
+    :param merge_io_wirevectors: if False, turn all N-bit IO wirevectors
+        into N 1-bit IO wirevectors (i.e. don't maintain interface).
+    :param block: The block you want to synthesize.
     :return: The newly synthesized block (of type PostSynthesisBlock).
 
     Takes as input a block (default to working block) and creates a new
@@ -368,7 +372,10 @@ def synthesize(update_working_block=True, block=None):
     the individual bits and memories (read and write ports) which
     require the reassembly and disassembly of the wirevectors immediately
     before and after. These are the only two places where 'c' and 's' ops
-    should exist.
+    should exist. If merge_io_vectors is False, then these individual
+    bits are not reassembled and disassembled before and after, and so no
+    'c' and 's' ops will exist. Instead, they will be named <name>[n],
+    where n is the bit number of original wire to which it corresponds.
 
     The block that results from synthesis is actually of type
     "PostSynthesisBlock" which contains a mapping from the original inputs
@@ -384,7 +391,9 @@ def synthesize(update_working_block=True, block=None):
 
     block_out = PostSynthBlock()
     # resulting block should only have one of a restricted set of net ops
-    block_out.legal_ops = set('~&|^nrwcsm@')
+    block_out.legal_ops = set('~&|^nrwm@')
+    if merge_io_vectors:
+        block_out.legal_ops.update(set('cs'))
     wirevector_map = {}  # map from (vector,index) -> new_wire
 
     with set_working_block(block_out, no_sanity_check=True):
@@ -399,6 +408,11 @@ def synthesize(update_working_block=True, block=None):
                 ('>', _basic_gt)]:
             net_transform(_replace_op(op, fun), block_in)
 
+        # This is a map from the cloned io wirevector created in copy_block,
+        # to the original io wirevector found in block_pre. We use it to create
+        # the block_out.io_map that is returned to the user.
+        orig_io_map = {temp: orig for orig, temp in block_in.io_map.items()}
+
         # Next, create all of the new wires for the new block
         # from the original wires and store them in the wirevector_map
         # for reference.
@@ -409,21 +423,31 @@ def synthesize(update_working_block=True, block=None):
                     new_val = (wirevector.val >> i) & 0x1
                     new_wirevector = Const(bitwidth=1, val=new_val)
                 elif isinstance(wirevector, (Input, Output)):
-                    new_wirevector = WireVector(name="tmp_" + new_name, bitwidth=1)
+                    if merge_io_vectors:
+                        new_wirevector = WireVector(name="tmp_" + new_name, bitwidth=1)
+                    else:
+                        # Creating N 1-bit io wires for a given single N-bit io wire.
+                        new_name = wirevector.name
+                        if len(wirevector) > 1:
+                            new_name += '[' + str(i) + ']'
+                        new_wirevector = wirevector.__class__(name=new_name, bitwidth=1)
+                        block_out.io_map[orig_io_map[wirevector]] = new_wirevector
                 else:
                     new_wirevector = wirevector.__class__(name=new_name, bitwidth=1)
                 wirevector_map[(wirevector, i)] = new_wirevector
 
         # Now connect up the inputs and outputs to maintain the interface
-        for wirevector in block_in.wirevector_subset(Input):
-            input_vector = Input(name=wirevector.name, bitwidth=len(wirevector))
-            for i in range(len(wirevector)):
-                wirevector_map[(wirevector, i)] <<= input_vector[i]
-        for wirevector in block_in.wirevector_subset(Output):
-            output_vector = Output(name=wirevector.name, bitwidth=len(wirevector))
-            output_bits = [wirevector_map[(wirevector, i)]
-                           for i in range(len(output_vector))]
-            output_vector <<= concat_list(output_bits)
+        if merge_io_vectors:
+            for wirevector in block_in.wirevector_subset(Input):
+                input_vector = Input(name=wirevector.name, bitwidth=len(wirevector))
+                for i in range(len(wirevector)):
+                    wirevector_map[(wirevector, i)] <<= input_vector[i]
+                block_out.io_map[orig_io_map[wirevector]] = [input_vector]
+            for wirevector in block_in.wirevector_subset(Output):
+                output_vector = Output(name=wirevector.name, bitwidth=len(wirevector))
+                output_bits = [wirevector_map[(wirevector, i)] for i in range(len(output_vector))]
+                output_vector <<= concat_list(output_bits)
+                block_out.io_map[orig_io_map[wirevector]] = [output_vector]
 
         # Now that we have all the wires built and mapped, walk all the blocks
         # and map the logic to the equivalent set of primitives in the system

pyrtl/transform.py

@@ -194,6 +194,7 @@ def copy_block(block=None, update_working_block=True):
     for net in block_in.logic:
         _copy_net(block_out, net, temp_wv_map, mems)
     block_out.mem_map = mems
+    block_out.io_map = {io: w for io, w in temp_wv_map.items() if isinstance(io, (Input, Output))}
 
     if update_working_block:
         set_working_block(block_out)

tests/test_passes.py

@@ -1,6 +1,7 @@
 from __future__ import print_function, unicode_literals, absolute_import
 
 import unittest
+from unittest.main import main
 import six
 import operator
 import os
@@ -70,6 +71,93 @@ def test_mux_simulation(self):
         self.check_trace('r 04213756\n')
 
 
+class TestIOInterfaceSynthesis(unittest.TestCase):
+    def setUp(self):
+        pyrtl.reset_working_block()
+        a, b = pyrtl.input_list('a/4 b/4')
+        o = pyrtl.Output(5, 'o')
+        o <<= a + b
+
+    def check_merged_names(self, block):
+        inputs = block.wirevector_subset(pyrtl.Input)
+        outputs = block.wirevector_subset(pyrtl.Output)
+        self.assertEqual({w.name for w in inputs}, {'a', 'b'})
+        self.assertEqual({w.name for w in outputs}, {'o'})
+
+    def check_unmerged_names(self, block):
+        inputs = block.wirevector_subset(pyrtl.Input)
+        outputs = block.wirevector_subset(pyrtl.Output)
+        self.assertEqual(
+            {w.name for w in inputs},
+            {'a[0]', 'a[1]', 'a[2]', 'a[3]', 'b[0]', 'b[1]', 'b[2]', 'b[3]'}
+        )
+        self.assertEqual(
+            {w.name for w in outputs},
+            {'o[0]', 'o[1]', 'o[2]', 'o[3]', 'o[4]'}
+        )
+
+    def test_synthesize_merged_io_names_correct(self):
+        pyrtl.synthesize()
+        self.check_merged_names(pyrtl.working_block())
+
+    def test_synthesize_merged_io_mapped_correctly(self):
+        old_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
+        pyrtl.synthesize()
+        new_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
+        for oi in old_io:
+            for ni in new_io:
+                if oi.name == ni.name:
+                    self.assertEqual(pyrtl.working_block().io_map[oi], [ni])
+
+    def test_synthesize_merged_io_simulates_correctly(self):
+        pyrtl.synthesize()
+        sim = pyrtl.Simulation()
+        sim.step_multiple({
+            'a': [4, 6, 2, 3],
+            'b': [2, 9, 11, 4],
+        })
+        output = six.StringIO()
+        sim.tracer.print_trace(output, compact=True)
+        self.assertEqual(
+            output.getvalue(),
+            'a 4623\n'
+            'b 29114\n'
+            'o 615137\n'
+        )
+
+    def test_synthesize_unmerged_io_names_correct(self):
+        pyrtl.synthesize(merge_io_vectors=False)
+        self.check_unmerged_names(pyrtl.working_block())
+
+    def test_synthesize_unmerged_io_mapped_correctly(self):
+        old_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
+        pyrtl.synthesize()
+        new_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
+        for oi in old_io:
+            for ni in new_io:
+                if ni.name.startswith(oi.name):
+                    self.assertIn(ni, pyrtl.working_block().io_map[oi])
+
+    def test_synthesize_unmerged_io_simulates_correctly(self):
+        pyrtl.synthesize(merge_io_vectors=False)
+        sim = pyrtl.Simulation()
+        for (a, b) in [(4, 2), (6, 9), (2, 11), (3, 4)]:
+            args = {}
+            for ix in range(4):
+                args['a[' + str(ix) + ']'] = (a >> ix) & 1
+                args['b[' + str(ix) + ']'] = (b >> ix) & 1
+            sim.step(args)
+            expected = a + b
+            for ix in range(5):
+                out = sim.inspect('o[' + str(ix) + ']')
+                self.assertEqual(out, (expected >> ix) & 1)
+
+    def test_synthesize_does_not_update_working_block(self):
+        synth_block = pyrtl.synthesize(update_working_block=False, merge_io_vectors=False)
+        self.check_merged_names(pyrtl.working_block())
+        self.check_unmerged_names(synth_block)
+
+
 class TestMultiplierSynthesis(unittest.TestCase):
     def setUp(self):
         pyrtl.reset_working_block()