Merge pull request #321 from pllab/named-constants

Adding option to name constants

Author: timsherwood

pyrtl/inputoutput.py

@@ -558,7 +558,8 @@ def label(v):
         return v
 
     if isinstance(node, Const):
-        return '[label="%d", shape=circle, fillcolor=lightgrey]' % label(node.val)
+        name = node.name + ': ' if not node.name.startswith('const_') else ''
+        return '[label="%s", shape=circle, fillcolor=lightgrey]' % label(name + str(node.val))
     elif isinstance(node, Input):
         return '[label="%s", shape=invhouse, fillcolor=coral]' % label(node.name)
     elif isinstance(node, Output):

pyrtl/simulation.py

@@ -992,7 +992,7 @@ def __init__(self, wires_to_track=None, block=None):
         self.block = working_block(block)
 
         def is_internal_name(name):
-            return (name.startswith('tmp') or name.startswith('const')
+            return (name.startswith('tmp') or name.startswith('const_')
                     # or name.startswith('synth_')
                     or name.endswith("'"))
 

pyrtl/transform.py

@@ -179,7 +179,9 @@ def clone_wire(old_wire, name=None):
     same name in the same block is not allowed
     """
     if isinstance(old_wire, Const):
-        return Const(old_wire.val, old_wire.bitwidth)
+        if name is None:
+            return Const(old_wire.val, old_wire.bitwidth, name=old_wire.name)
+        return Const(old_wire.val, old_wire.bitwidth, name=name)
     else:
         if name is None:
             return old_wire.__class__(old_wire.bitwidth, name=old_wire.name)

pyrtl/wire.py

@@ -579,10 +579,10 @@ class Const(WireVector):
 
     _code = 'C'
 
-    def __init__(self, val, bitwidth=None, signed=False, block=None):
+    def __init__(self, val, bitwidth=None, name='', signed=False, block=None):
         """ Construct a constant implementation at initialization
 
-        :param int, bool, or str val: The value for the const wirevector
+        :param int, bool, or str val: the value for the const wirevector
         :param int: the desired bitwidth of the resulting const
         :param signed: specify if bits should be used for twos complement
         :return: a wirevector object representing a const wire
@@ -611,7 +611,7 @@ def __init__(self, val, bitwidth=None, signed=False, block=None):
                 'constant %d returned by infer_val_and_bitwidth somehow not fitting in %d bits'
                 % (num, bitwidth))
 
-        name = _constIndexer.make_valid_string() + '_' + str(val)
+        name = name if name else _constIndexer.make_valid_string() + '_' + str(val)
 
         super(Const, self).__init__(bitwidth=bitwidth, name=name, block=block)
         # add the member "val" to track the value of the constant

tests/test_simulation.py

@@ -300,6 +300,25 @@ class MyEnum(IntEnum):
         sim.step({'i': MyEnum.C})
         self.assertEqual(sim.inspect(o), 1)
 
+    def test_named_consts(self):
+        in1 = pyrtl.Input(8, "in1")
+        c1 = pyrtl.Const(1, 1, "c1")
+        out1 = pyrtl.Output(16, "out1")
+        out1 <<= in1 + c1
+        sim_trace = pyrtl.SimulationTrace()
+        sim = self.sim(tracer=sim_trace)
+        for i in range(10):
+            sim.step({
+                'in1': 2 * i,
+            })
+        correct_outp = (" --- Values in base 10 ---\n"
+                        "c1    1  1  1  1  1  1  1  1  1  1\n"
+                        "in1   0  2  4  6  8 10 12 14 16 18\n"
+                        "out1  1  3  5  7  9 11 13 15 17 19\n")
+        output = six.StringIO()
+        sim_trace.print_trace(output)
+        self.assertEqual(output.getvalue(), correct_outp)
+
 
 class SimInputValidationBase(unittest.TestCase):
     def setUp(self):

tests/test_transform.py

@@ -24,6 +24,23 @@ def num_wire_of_type(self, wiretype, num, block=None):
         self.assertEquals(len(block.wirevector_subset(wiretype)), num)
 
 
+class WireMemoryNameTestCases(unittest.TestCase):
+    def setUp(self):
+        pyrtl.reset_working_block()
+
+    def name_wires(self, names, block=None):
+        block = pyrtl.working_block()
+        names = set(names.split(' '))
+        for n in names:
+            self.assertIn(n, block.wirevector_by_name)
+
+    def name_memories(self, names, block=None):
+        block = pyrtl.working_block()
+        names = set(names.split(' '))
+        for n in names:
+            self.assertIn(n, block.memblock_by_name)
+
+
 def insert_random_inversions(rate=0.5):
     """
     an example transform that can be used for testing
@@ -57,7 +74,7 @@ def test_randomly_replace(self):
         self.assertIsNot(new_and_net.dests[0], o)
 
 
-class TestCopyBlock(NetWireNumTestCases):
+class TestCopyBlock(NetWireNumTestCases, WireMemoryNameTestCases):
     def num_memories(self, mems_expected, block):
         memories = set()
         for net in block.logic_subset('m@'):
@@ -70,27 +87,31 @@ def test_blank(self):
         self.assert_num_wires(0, block)
 
     def test_block(self):
-        a = pyrtl.Const(23)
-        b = pyrtl.Input(5)
-        o = pyrtl.Output(5)
+        a = pyrtl.Const(23, name='a')
+        b = pyrtl.Input(5, name='b')
+        o = pyrtl.Output(5, name='o')
         o <<= ~a & b
 
         old_block = pyrtl.working_block()
         old_block.sanity_check()
         self.assert_num_wires(5, old_block)
         self.assert_num_net(3, old_block)
 
+        self.name_wires('a b o', old_block)
+
         new_block = transform.copy_block()
         new_block.sanity_check()
         self.assert_num_wires(5, new_block)
-        self.assert_num_net(3, old_block)
+        self.assert_num_net(3, new_block)
+
+        self.name_wires('a b o', new_block)
 
     def test_copy_mem(self):
         ins = [pyrtl.Input(5) for i in range(4)]
         out = pyrtl.Output(5)
 
-        mem1 = pyrtl.MemBlock(5, 5)
-        mem2 = pyrtl.MemBlock(5, 5)
+        mem1 = pyrtl.MemBlock(5, 5, name='mem1')
+        mem2 = pyrtl.MemBlock(5, 5, name='mem2')
 
         mem1_o1 = mem1[ins[0]]
         mem1[ins[1]] <<= ins[2]
@@ -104,12 +125,16 @@ def test_copy_mem(self):
         self.num_net_of_type('&', 1, old_block)
         self.num_memories(2, old_block)
 
+        self.name_memories('mem1 mem2', old_block)
+
         new_block = transform.copy_block()
         self.num_net_of_type('m', 2, new_block)
         self.num_net_of_type('@', 1, new_block)
         self.num_net_of_type('&', 1, new_block)
         self.num_memories(2, new_block)
 
+        self.name_memories('mem1 mem2', new_block)
+
 
 class TestFastWireReplace(unittest.TestCase):
     def setUp(self):
@@ -191,3 +216,6 @@ def probe_cond(wire):
     transform_examples.probe_wire_if(probe_cond)
     probe.assert_called_once_with(test_wire)
 """
+
+if __name__ == "__main__":
+    unittest.main()

tests/test_verilog.py

@@ -15,15 +15,15 @@
 
     wire[3:0] const_0_12;
     wire[2:0] const_1_3;
-    wire[5:0] const_2_38;
+    wire[5:0] k;
     wire[12:0] tmp0;
 
     // Combinational
     assign const_0_12 = 12;
     assign const_1_3 = 3;
-    assign const_2_38 = 38;
+    assign k = 38;
     assign o = tmp0;
-    assign tmp0 = {const_0_12, const_1_3, const_2_38};
+    assign tmp0 = {const_0_12, const_1_3, k};
 
 endmodule
 
@@ -642,7 +642,7 @@ def test_romblock_does_not_throw_error(self):
     def test_textual_consistency_small(self):
         i = pyrtl.Const(0b1100)
         j = pyrtl.Const(0b011, bitwidth=3)
-        k = pyrtl.Const(0b100110)
+        k = pyrtl.Const(0b100110, name='k')
         o = pyrtl.Output(13, 'o')
         o <<= pyrtl.concat(i, j, k)
 

tests/test_wire.py

@@ -316,6 +316,18 @@ def test_assignment(self):
             c = pyrtl.Const(4)
             c <<= 3
 
+    def test_named(self):
+        block = pyrtl.working_block()
+        c = pyrtl.Const(20, name="archid")
+        self.assertIn("archid", block.wirevector_by_name)
+        self.assertIn(c, block.wirevector_set)
+        self.assertEqual(c.val, 20)
+        c.name = "vendorid"
+        self.assertNotIn("archid", block.wirevector_by_name)
+        self.assertIn("vendorid", block.wirevector_by_name)
+        self.assertIn(c, block.wirevector_set)
+        self.assertEqual(c.val, 20)
+
     def check_const(self, val_in, expected_val, expected_bitwidth, **kargs):
         c = pyrtl.Const(val_in, **kargs)
         self.assertEqual(c.val, expected_val)