Merge pull request #345 from pllab/synthesis-update

Fix post-synth passes test; add reg_map for tracking registers post-synthesis

Author: mdko

pyrtl/core.py

@@ -730,11 +730,21 @@ def sanity_check_net(self, net):
 class PostSynthBlock(Block):
     """ This is a block with extra metadata required to maintain the
     pre-synthesis interface during post-synthesis.
+
+    It currently holds the following instance attributes:
+
+    * *.io_map*: a map from old IO wirevector to a list of new IO wirevectors it maps to;
+        this is a list because for unmerged io vectors, each old N-bit IO wirevector maps
+        to N new 1-bit IO wirevectors.
+    * *.reg_map*: a map from old register to a list of new registers; a list because post-synthesis,
+        each N-bit register has been mapped to N 1-bit registers
+    * *.mem_map*: a map from old memory block to the new memory block
     """
 
     def __init__(self):
         super(PostSynthBlock, self).__init__()
-        self.io_map = {}
+        self.io_map = collections.defaultdict(list)
+        self.reg_map = collections.defaultdict(list)
         self.mem_map = {}
 
 

pyrtl/passes.py

@@ -15,7 +15,8 @@
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
 from .wire import WireVector, Input, Output, Const, Register
 from .transform import net_transform, _get_new_block_mem_instance, copy_block, replace_wires
-from . import transform  # transform.all_nets looks better than all_nets
+from . import transform
+from pyrtl import wire  # transform.all_nets looks better than all_nets
 
 
 # --------------------------------------------------------------------
@@ -411,6 +412,7 @@ def synthesize(update_working_block=True, merge_io_vectors=True, block=None):
         # to the original io wirevector found in block_pre. We use it to create
         # the block_out.io_map that is returned to the user.
         orig_io_map = {temp: orig for orig, temp in block_in.io_map.items()}
+        orig_reg_map = {temp: orig for orig, temp in block_in.reg_map.items()}
 
         # Next, create all of the new wires for the new block
         # from the original wires and store them in the wirevector_map
@@ -430,9 +432,11 @@ def synthesize(update_working_block=True, merge_io_vectors=True, block=None):
                         if len(wirevector) > 1:
                             new_name += '[' + str(i) + ']'
                         new_wirevector = wirevector.__class__(name=new_name, bitwidth=1)
-                        block_out.io_map[orig_io_map[wirevector]] = new_wirevector
+                        block_out.io_map[orig_io_map[wirevector]].append(new_wirevector)
                 else:
                     new_wirevector = wirevector.__class__(name=new_name, bitwidth=1)
+                    if isinstance(wirevector, Register):
+                        block_out.reg_map[orig_reg_map[wirevector]].append(new_wirevector)
                 wirevector_map[(wirevector, i)] = new_wirevector
 
         # Now connect up the inputs and outputs to maintain the interface
@@ -441,12 +445,12 @@ def synthesize(update_working_block=True, merge_io_vectors=True, block=None):
                 input_vector = Input(name=wirevector.name, bitwidth=len(wirevector))
                 for i in range(len(wirevector)):
                     wirevector_map[(wirevector, i)] <<= input_vector[i]
-                block_out.io_map[orig_io_map[wirevector]] = [input_vector]
+                block_out.io_map[orig_io_map[wirevector]].append(input_vector)
             for wirevector in block_in.wirevector_subset(Output):
                 output_vector = Output(name=wirevector.name, bitwidth=len(wirevector))
                 output_bits = [wirevector_map[(wirevector, i)] for i in range(len(output_vector))]
                 output_vector <<= concat_list(output_bits)
-                block_out.io_map[orig_io_map[wirevector]] = [output_vector]
+                block_out.io_map[orig_io_map[wirevector]].append(output_vector)
 
         # Now that we have all the wires built and mapped, walk all the blocks
         # and map the logic to the equivalent set of primitives in the system

pyrtl/transform.py

@@ -195,6 +195,7 @@ def copy_block(block=None, update_working_block=True):
         _copy_net(block_out, net, temp_wv_map, mems)
     block_out.mem_map = mems
     block_out.io_map = {io: w for io, w in temp_wv_map.items() if isinstance(io, (Input, Output))}
+    block_out.reg_map = {r: w for r, w, in temp_wv_map.items() if isinstance(r, Register)}
 
     if update_working_block:
         set_working_block(block_out)

tests/test_passes.py

@@ -69,6 +69,15 @@ def test_mux_simulation(self):
         self.r.next <<= pyrtl.mux(self.r, 4, 3, 1, 7, 2, 6, 0, 5)
         self.check_trace('r 04213756\n')
 
+    def test_synthesize_regs_mapped_correctly(self):
+        r2 = pyrtl.Register(5)
+        self.r.next <<= ~ self.r
+        r2.next <<= self.r + 1
+        synth_block = pyrtl.synthesize()
+        self.assertEqual(len(synth_block.reg_map), 2)
+        self.assertEqual(len(synth_block.reg_map[self.r]), len(self.r))
+        self.assertEqual(len(synth_block.reg_map[r2]), len(r2))
+
 
 class TestIOInterfaceSynthesis(unittest.TestCase):
     def setUp(self):
@@ -104,9 +113,11 @@ def test_synthesize_merged_io_mapped_correctly(self):
         pyrtl.synthesize()
         new_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
         for oi in old_io:
+            io_list = pyrtl.working_block().io_map[oi]
+            self.assertEqual(len(io_list), 1)
             for ni in new_io:
                 if oi.name == ni.name:
-                    self.assertEqual(pyrtl.working_block().io_map[oi], [ni])
+                    self.assertEqual(io_list, [ni])
 
     def test_synthesize_merged_io_simulates_correctly(self):
         pyrtl.synthesize()
@@ -130,12 +141,16 @@ def test_synthesize_unmerged_io_names_correct(self):
 
     def test_synthesize_unmerged_io_mapped_correctly(self):
         old_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
-        pyrtl.synthesize()
+        pyrtl.synthesize(merge_io_vectors=False)
         new_io = pyrtl.working_block().wirevector_subset((pyrtl.Input, pyrtl.Output))
         for oi in old_io:
+            io_list = [w.name for w in pyrtl.working_block().io_map[oi]]
+            self.assertEqual(len(io_list), len(oi))
             for ni in new_io:
                 if ni.name.startswith(oi.name):
-                    self.assertIn(ni, pyrtl.working_block().io_map[oi])
+                    # Dev note: comparing names because comparing wires (e.g. list/set inclusion)
+                    # creates an '=' net, which is definitely not what we want here.
+                    self.assertIn(ni.name, io_list)
 
     def test_synthesize_unmerged_io_simulates_correctly(self):
         pyrtl.synthesize(merge_io_vectors=False)