Merge branch 'development' of https://github.com/UCSBarchlab/PyRTL into development

Author: timsherwood

pyrtl/importexport.py

@@ -325,17 +325,21 @@ def twire(w):
             output_wire = twire(netio[2])
             output_wire <<= twire(netio[0]) | twire(netio[1])  # or gate
         elif command['cover_list'].asList() == ['0-', '1', '-0', '1']:
+            # nand is not really a PyRTL primitive and so should only be added to a netlist
+            # via a call to nand_synth(). We instead convert it to ~(a & b) rather than
+            # (~a | ~b) as would be generated if handled by the else case below.
             output_wire = twire(netio[2])
-            output_wire <<= twire(netio[0]).nand(twire(netio[1]))  # nand gate
+            output_wire <<= ~(twire(netio[0]) & twire(netio[1]))  # nand gate -> not+and gates
         elif command['cover_list'].asList() == ['10', '1', '01', '1']:
             output_wire = twire(netio[2])
             output_wire <<= twire(netio[0]) ^ twire(netio[1])  # xor gate
         else:
             # Although the following is fully generic and thus encompasses all of the
             # special cases after the simple wire case above, we leave the above in because
             # they are commonly found and lead to a slightly cleaner (though equivalent) netlist,
-            # because we can use nand/xor primitives, or avoid the extra fluff of concat/select
-            # wires that might be created implicitly as part of rtl_all/rtl_any.
+            # because we can use the xor primitive/save a gate when converting the nand, or avoid
+            # the extra fluff of concat/select wires that might be created implicitly as part of
+            # rtl_all/rtl_any.
             def convert_val(ix, val):
                 wire = twire(netio[ix])
                 if val == '0':
@@ -758,22 +762,25 @@ def _to_verilog_memories(file, block, varname):
     memories = {n.op_param[1] for n in block.logic_subset('m@')}
     for m in sorted(memories, key=lambda m: m.id):
         print('    // Memory mem_{}: {}'.format(m.id, m.name), file=file)
-        print('    always @(posedge clk)', file=file)
-        print('    begin', file=file)
-        for net in _net_sorted(block.logic_subset('@'), varname):
-            if net.op_param[1] == m:
+        writes = [net for net in _net_sorted(block.logic_subset('@'), varname)
+                  if net.op_param[1] == m]
+        if writes:
+            print('    always @(posedge clk)', file=file)
+            print('    begin', file=file)
+            for net in writes:
                 t = (varname(net.args[2]), net.op_param[0],
                      varname(net.args[0]), varname(net.args[1]))
                 print(('        if (%s) begin\n'
                        '            mem_%s[%s] <= %s;\n'
                        '        end') % t, file=file)
-        print('    end', file=file)
-        for net in _net_sorted(block.logic_subset('m'), varname):
-            if net.op_param[1] == m:
-                dest = varname(net.dests[0])
-                m_id = net.op_param[0]
-                index = varname(net.args[0])
-                print('    assign {:s} = mem_{}[{:s}];'.format(dest, m_id, index), file=file)
+            print('    end', file=file)
+        reads = [net for net in _net_sorted(block.logic_subset('m'), varname)
+                 if net.op_param[1] == m]
+        for net in reads:
+            dest = varname(net.dests[0])
+            m_id = net.op_param[0]
+            index = varname(net.args[0])
+            print('    assign {:s} = mem_{}[{:s}];'.format(dest, m_id, index), file=file)
         print('', file=file)
 
 

tests/test_importexport.py

@@ -663,7 +663,9 @@ def test_blif_or_gate_correct(self):
         })
         self.assertEqual(sim.tracer.trace['o'], [0, 1, 1, 1])
 
-    def test_blif_nand_gate_correct(self):
+    def test_blif_nand_gate_to_primitives_correct(self):
+        # This tests that there should be no NAND gates generated during BLIF import;
+        # they should be converted to AND+NOT.
         blif = """\
         .model Top
         .inputs a b
@@ -675,7 +677,9 @@ def test_blif_nand_gate_correct(self):
         """
         pyrtl.input_from_blif(blif)
         block = pyrtl.working_block()
-        self.assertEqual(len(block.logic_subset('n')), 1)
+        self.assertEqual(len(block.logic_subset('n')), 0)
+        self.assertEqual(len(block.logic_subset('&')), 1)
+        self.assertEqual(len(block.logic_subset('~')), 1)
         sim = pyrtl.Simulation()
         sim.step_multiple({
             'a': '0011',
@@ -1384,6 +1388,56 @@ def test_blif_nor_gate_correct(self):
 """
 
 
+verilog_output_mems_with_no_writes = """\
+// Generated automatically via PyRTL
+// As one initial test of synthesis, map to FPGA with:
+//   yosys -p "synth_xilinx -top toplevel" thisfile.v
+
+module toplevel(clk, rst, in1, out1);
+    input clk;
+    input rst;
+    input[2:0] in1;
+    output[7:0] out1;
+
+    reg[7:0] mem_0[7:0]; //tmp0
+    reg[7:0] mem_1[255:0]; //tmp1
+
+    wire const_0_1;
+    wire[7:0] const_1_42;
+    wire[7:0] tmp2;
+
+    initial begin
+        mem_0[0]=8'ha;
+        mem_0[1]=8'h14;
+        mem_0[2]=8'h1e;
+        mem_0[3]=8'h28;
+        mem_0[4]=8'h32;
+        mem_0[5]=8'h3c;
+        mem_0[6]=8'h0;
+        mem_0[7]=8'h0;
+    end
+
+    // Combinational
+    assign const_0_1 = 1;
+    assign const_1_42 = 42;
+    assign out1 = tmp2;
+
+    // Memory mem_0: tmp0
+    assign tmp2 = mem_0[in1];
+
+    // Memory mem_1: tmp1
+    always @(posedge clk)
+    begin
+        if (const_0_1) begin
+            mem_1[tmp2] <= const_1_42;
+        end
+    end
+
+endmodule
+
+"""
+
+
 verilog_output_counter_no_reset = """\
 // Generated automatically via PyRTL
 // As one initial test of synthesis, map to FPGA with:
@@ -1568,6 +1622,21 @@ def test_textual_consistency_large(self):
 
         self.assertEqual(buffer.getvalue(), verilog_output_large)
 
+    def test_mems_with_no_writes(self):
+        rdata = {0: 10, 1: 20, 2: 30, 3: 40, 4: 50, 5: 60}
+        rom = pyrtl.RomBlock(8, 3, rdata, pad_with_zeros=True)
+        mem = pyrtl.MemBlock(8, 8)
+        in1 = pyrtl.Input(3, 'in1')
+        out1 = pyrtl.Output(8, 'out1')
+        w = rom[in1]
+        out1 <<= w
+        mem[w] <<= 42
+
+        buffer = io.StringIO()
+        pyrtl.output_to_verilog(buffer)
+
+        self.assertEqual(buffer.getvalue(), verilog_output_mems_with_no_writes)
+
     def check_counter_text(self, add_reset, expected):
         r = pyrtl.Register(4, reset_value=2)
         r.next <<= r + 1