consolidate visualization-related functions into single file, import-export-related functions into separate single file

Author: mdko

docs/export.rst

@@ -6,14 +6,14 @@ Exporting and Importing Designs
 Exporting Hardware Designs
 --------------------------
 
-.. autofunction:: pyrtl.verilog.output_to_verilog
+.. autofunction:: pyrtl.inputoutput.output_to_verilog
 
 .. autofunction:: pyrtl.inputoutput.output_to_firrtl
 
 Exporting Testbenches
 ------------------------
 
-.. autofunction:: pyrtl.verilog.output_verilog_testbench
+.. autofunction:: pyrtl.inputoutput.output_verilog_testbench
 
 
 Importing Verilog
@@ -25,12 +25,12 @@ Importing Verilog
 Outputting for Visualization
 ---------------------------
 
-.. autofunction:: pyrtl.inputoutput.output_to_trivialgraph
-.. autofunction:: pyrtl.inputoutput.output_to_graphviz
-.. autofunction:: pyrtl.inputoutput.graphviz_detailed_namer
-.. autofunction:: pyrtl.inputoutput.output_to_svg
-.. autofunction:: pyrtl.inputoutput.block_to_graphviz_string
-.. autofunction:: pyrtl.inputoutput.block_to_svg
-.. autofunction:: pyrtl.inputoutput.trace_to_html
-.. autofunction:: pyrtl.inputoutput.net_graph
+.. autofunction:: pyrtl.visualization.output_to_trivialgraph
+.. autofunction:: pyrtl.visualization.output_to_graphviz
+.. autofunction:: pyrtl.visualization.graphviz_detailed_namer
+.. autofunction:: pyrtl.visualization.output_to_svg
+.. autofunction:: pyrtl.visualization.block_to_graphviz_string
+.. autofunction:: pyrtl.visualization.block_to_svg
+.. autofunction:: pyrtl.visualization.trace_to_html
+.. autofunction:: pyrtl.visualization.net_graph
 

pyrtl/__init__.py

@@ -20,7 +20,6 @@
 from .wire import Register
 
 # helper functions
-
 from .helperfuncs import input_list
 from .helperfuncs import output_list
 from .helperfuncs import register_list
@@ -67,7 +66,6 @@
 from .corecircuits import shift_left_logical
 from .corecircuits import shift_right_logical
 
-
 # memory blocks
 from .memory import MemBlock
 from .memory import RomBlock
@@ -83,22 +81,22 @@
 from .simulation import SimulationTrace
 from .compilesim import CompiledSimulation
 
+# block visualization output formats
+from .visualization import output_to_trivialgraph
+from .visualization import graphviz_detailed_namer
+from .visualization import output_to_graphviz
+from .visualization import output_to_svg
+from .visualization import block_to_graphviz_string
+from .visualization import block_to_svg
+from .visualization import trace_to_html
+from .visualization import net_graph
+
 # input and output to file format routines
+from .inputoutput import output_to_verilog
+from .inputoutput import OutputToVerilog
+from .inputoutput import output_verilog_testbench
 from .inputoutput import input_from_blif
-from .inputoutput import output_to_trivialgraph
-from .inputoutput import graphviz_detailed_namer
-from .inputoutput import output_to_graphviz
-from .inputoutput import output_to_svg
 from .inputoutput import output_to_firrtl
-from .inputoutput import block_to_graphviz_string
-from .inputoutput import block_to_svg
-from .inputoutput import trace_to_html
-from .inputoutput import net_graph
-
-# extraction to verilog and verilog testbench
-from .verilog import output_to_verilog
-from .verilog import OutputToVerilog
-from .verilog import output_verilog_testbench
 
 # different analysis and transform passes
 from .passes import common_subexp_elimination

pyrtl/analysis/estimate.py

@@ -16,7 +16,7 @@
 from ..core import working_block
 from ..wire import Input, Const, Register
 from ..pyrtlexceptions import PyrtlError, PyrtlInternalError
-from ..verilog import output_to_verilog
+from ..inputoutput import output_to_verilog
 from ..memory import RomBlock
 from ..helperfuncs import _currently_in_jupyter_notebook, _print_netlist_latex
 

pyrtl/core.py

@@ -460,7 +460,7 @@ def add_wire_dst(edge, node):
 
     def _repr_svg_(self):
         """ IPython display support for Block. """
-        from .inputoutput import block_to_svg
+        from .visualization import block_to_svg
         return block_to_svg(self)
 
     def __iter__(self):