Fixed formatting errors

Author: devmam999

tests/test_importexport.py

@@ -1308,17 +1308,18 @@ def test_bit_slice_inputs(self):
         # only has one user and just passes through ``c``, because that user is a
         # bit-slice.
         self.assertTrue("assign tmp3 = c" in buffer.getvalue())
+
     def test_custom_module_name(self):
-        a, b = pyrtl.Input(1, 'a'), pyrtl.Input(1, 'b')
-        out = pyrtl.Output(name='out')
+        a, b = pyrtl.Input(1, "a"), pyrtl.Input(1, "b")
+        out = pyrtl.Output(name="out")
         out <<= a & b
 
         buf = io.StringIO()
-        pyrtl.output_to_verilog(buf, module_name='custom_top')
+        pyrtl.output_to_verilog(buf, module_name="custom_top")
         text = buf.getvalue()
 
-        self.assertIn('module custom_top', text)
-        self.assertNotIn('module toplevel', text)
+        self.assertIn("module custom_top", text)
+        self.assertNotIn("module toplevel", text)
 
 
 verilog_input_counter = """\
@@ -1664,6 +1665,7 @@ def test_only_initialize_memblocks(self):
         pyrtl.output_verilog_testbench(buffer, add_reset=False)
         # The testbench should not touch the RomBlock.
         self.assertTrue("my_rom" not in buffer.getvalue())
+
     def test_custom_module_name_testbench(self):
         # Minimal design
         a, b = pyrtl.Input(1, "a"), pyrtl.Input(1, "b")
@@ -1680,7 +1682,6 @@ def test_custom_module_name_testbench(self):
         self.assertNotIn("toplevel block(", text)
 
 
-
 firrtl_output_concat_test = """\
 circuit Example :
   module Example :
@@ -2295,6 +2296,5 @@ def test_bench_with_same_io_name(self):
         self.check_io(pyrtl.Output, ["tmp3", "G4"])
 
 
-
 if __name__ == "__main__":
     unittest.main()