Skip to content

Commit d1ec3fb

Browse files
committed
Fix FastSimulation to work with IntEnums
1 parent 2587b1c commit d1ec3fb

File tree

2 files changed

+27
-1
lines changed

2 files changed

+27
-1
lines changed

pyrtl/simulation.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -710,7 +710,7 @@ def _arg_varname(self, wire):
710710
if isinstance(wire, (Input, Register)):
711711
return 'd[' + repr(wire.name) + ']' # passed in
712712
elif isinstance(wire, Const):
713-
return str(wire.val) # hardcoded
713+
return str(int(wire.val)) # hardcoded
714714
else:
715715
return self._varname(wire)
716716

tests/test_simulation.py

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -274,6 +274,32 @@ def test_fastsim_wire_names(self):
274274
sim_trace.print_trace(output)
275275
self.assertEqual(output.getvalue(), correct_outp)
276276

277+
def test_consts_from_int_enums(self):
278+
from enum import IntEnum
279+
280+
class MyEnum(IntEnum):
281+
A = 0
282+
B = 1
283+
C = 3
284+
285+
i = pyrtl.Input(max(MyEnum).bit_length(), 'i')
286+
o = pyrtl.Output(1, 'o')
287+
with pyrtl.conditional_assignment:
288+
with (i == MyEnum.A) | (i == MyEnum.B):
289+
o |= 0
290+
with pyrtl.otherwise:
291+
o |= 1
292+
293+
trace = pyrtl.SimulationTrace()
294+
sim = self.sim(tracer=trace)
295+
296+
sim.step({'i': MyEnum.A})
297+
self.assertEqual(sim.inspect(o), 0)
298+
sim.step({'i': MyEnum.B})
299+
self.assertEqual(sim.inspect(o), 0)
300+
sim.step({'i': MyEnum.C})
301+
self.assertEqual(sim.inspect(o), 1)
302+
277303

278304
class SimInputValidationBase(unittest.TestCase):
279305
def setUp(self):

0 commit comments

Comments
 (0)