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lines changed Original file line number Diff line number Diff line change @@ -710,7 +710,7 @@ def _arg_varname(self, wire):
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if isinstance (wire , (Input , Register )):
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return 'd[' + repr (wire .name ) + ']' # passed in
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elif isinstance (wire , Const ):
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- return str (wire .val ) # hardcoded
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+ return str (int ( wire .val ) ) # hardcoded
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else :
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return self ._varname (wire )
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Original file line number Diff line number Diff line change @@ -274,6 +274,32 @@ def test_fastsim_wire_names(self):
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sim_trace .print_trace (output )
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self .assertEqual (output .getvalue (), correct_outp )
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+ def test_consts_from_int_enums (self ):
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+ from enum import IntEnum
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+
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+ class MyEnum (IntEnum ):
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+ A = 0
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+ B = 1
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+ C = 3
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+
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+ i = pyrtl .Input (max (MyEnum ).bit_length (), 'i' )
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+ o = pyrtl .Output (1 , 'o' )
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+ with pyrtl .conditional_assignment :
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+ with (i == MyEnum .A ) | (i == MyEnum .B ):
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+ o |= 0
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+ with pyrtl .otherwise :
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+ o |= 1
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+
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+ trace = pyrtl .SimulationTrace ()
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+ sim = self .sim (tracer = trace )
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+
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+ sim .step ({'i' : MyEnum .A })
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+ self .assertEqual (sim .inspect (o ), 0 )
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+ sim .step ({'i' : MyEnum .B })
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+ self .assertEqual (sim .inspect (o ), 0 )
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+ sim .step ({'i' : MyEnum .C })
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+ self .assertEqual (sim .inspect (o ), 1 )
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+
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class SimInputValidationBase (unittest .TestCase ):
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def setUp (self ):
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