Simplify Yosys script

Author: mdko

pyrtl/importexport.py

@@ -446,7 +446,7 @@ def input_from_verilog(verilog, clock_name='clk', toplevel=None, leave_in_dir=No
 
     Note: This function is essentially a wrapper for `input_from_blif()`, with the added convenience
     of turning the Verilog into BLIF for import for you. This function passes a set of commands to
-    Yosys as a script that is normally produces BLIF files that can be successuflly imported into
+    Yosys as a script that normally produces BLIF files that can be successuflly imported into
     PyRTL via `input_from_blif()`. If the Yosys conversion fails here, we recommend you create your
     own custom Yosys script to try and produce BLIF yourself.  Then you can import BLIF directly via
     `input_from_blif()`.
@@ -469,15 +469,6 @@ def input_from_verilog(verilog, clock_name='clk', toplevel=None, leave_in_dir=No
         else:
             raise PyrtlError('input_from_verilog expecting either open file or string')
 
-    if toplevel is None:
-        module_lines = [line
-                        for line in verilog_string.split('\n')
-                        if ('module ' in line) and ('endmodule' not in line)]
-        if module_lines:
-            toplevel = re.match(r'\s*module\s+([^;(]*)', module_lines[0]).group(1).strip()
-        if toplevel is None:
-            raise PyrtlError('No module found in verilog file')
-
     block = working_block(block)
 
     # Create a temporary Verilog file
@@ -493,15 +484,15 @@ def input_from_verilog(verilog, clock_name='clk', toplevel=None, leave_in_dir=No
     yosys_arg_template = (
         "-p "
         "read_verilog %s; "
-        "hierarchy -check -top %s; "
-        "proc; opt; memory; opt; fsm; opt; "
-        "techmap; opt; "
+        "synth %s; "
         "setundef -zero -undriven; "
         "opt; "
         "write_blif %s; "
     )
 
-    yosys_arg = yosys_arg_template % (tmp_verilog_path, toplevel, tmp_blif_path)
+    yosys_arg = yosys_arg_template % (tmp_verilog_path,
+                                      ('-top ' + toplevel) if toplevel is not None else '-auto-top',
+                                      tmp_blif_path)
 
     try:
         os.close(temp_vd)

tests/test_importexport.py

@@ -1668,23 +1668,19 @@ def test_import_counter_with_reset(self):
         sim.step_multiple({'rst': '1000'})
         self.assertEqual(sim.tracer.trace['o'], [0, 2, 3, 4])
 
-    def test_import_multi_module_top_most_module(self):
+    def test_import_multi_module_specified_module(self):
         # Import foo module because occurs first in file
-        pyrtl.input_from_verilog(verilog_input_multi_module)
+        pyrtl.input_from_verilog(verilog_input_multi_module, toplevel="foo")
         sim = pyrtl.Simulation()
         sim.step_multiple({'a': '0011', 'b': '0101'})
         self.assertEqual(sim.tracer.trace['o'], [0, 1, 1, 2])
 
-    def test_import_multi_module_specified_module(self):
-        pyrtl.input_from_verilog(verilog_input_multi_module, toplevel='top')
+    def test_import_multi_module_auto_select_top_module(self):
+        pyrtl.input_from_verilog(verilog_input_multi_module)
         sim = pyrtl.Simulation()
         sim.step_multiple(nsteps=5)
         self.assertEqual(sim.tracer.trace['o'], [0, 2, 0, 2, 0])
 
-    def test_error_import_no_module(self):
-        with self.assertRaisesRegex(pyrtl.PyrtlError, "No module found in verilog file"):
-            pyrtl.input_from_verilog("")
-
     def test_error_import_bad_file(self):
         with self.assertRaisesRegex(pyrtl.PyrtlError,
                                     "input_from_verilog expecting either open file or string"):