Merge pull request #373 from pllab/iscas_bench_update

Rename ISCAS bench output wires if also an input

Author: mdko

pyrtl/importexport.py

@@ -12,7 +12,7 @@
 
 from .pyrtlexceptions import PyrtlError, PyrtlInternalError
 from .core import working_block, _NameSanitizer
-from .wire import WireVector, Input, Output, Const, Register
+from .wire import WireVector, Input, Output, Const, Register, next_tempvar_name
 from .corecircuits import concat_list
 from .memory import RomBlock
 from .passes import two_way_concat, one_bit_selects
@@ -1055,3 +1055,20 @@ def twire(name):
                 dst_wire <<= reg
             else:
                 raise PyrtlError("Unexpected gate {%s}" % cmd["gate"])
+
+    # Benchmarks like c1196, b18, etc. have inputs and outputs by the
+    # same name, that are therefore directly connected. This pass will
+    # rename the outputs so that this is still okay.
+    for o in block.wirevector_subset(Output):
+        inputs = [i for i in block.wirevector_subset(Input) if i.name == o.name]
+        if inputs:
+            if len(inputs) > 1:
+                raise PyrtlError("More than one input found with the name %s" % inputs[0].name)
+            i = inputs[0]
+            o_internal = twire(o.name)
+            o_internal <<= i
+            o.name = next_tempvar_name()
+            # Ensure the input is the one mapped by the original name
+            block.wirevector_by_name[i.name] = i
+            print("Found input and output wires with the same name. "
+                  "Output '%s' has now been renamed to '%s'." % (i.name, o.name))

tests/test_importexport.py

@@ -1,6 +1,7 @@
 import unittest
 import random
 import io
+import sys
 import six
 import pyrtl
 from pyrtl.importexport import _VerilogSanitizer
@@ -1875,6 +1876,17 @@ def test_textual_consistency_selects(self):
 G13 = NOR(G2, G12)
 """
 
+example_bench_with_io_same_name = """\
+INPUT(G1)
+INPUT(G2)
+INPUT(G3)
+
+OUTPUT(G3)
+OUTPUT(G4)
+
+G4 = OR(G1, G2)
+"""
+
 
 class TestInputISCASBench(unittest.TestCase):
     # NOTE: number of inverters = number of original inverters + number of NORs, since
@@ -1950,6 +1962,22 @@ def test_simulation_bench(self):
         trace.print_trace(output, compact=True)
         self.assertEqual(output.getvalue(), correct_output)
 
+    def test_bench_with_same_io_name(self):
+        output = six.StringIO()
+        sys.stdout = output
+        pyrtl.input_from_iscas_bench(example_bench_with_io_same_name)
+        sys.stdout = sys.__stdout__
+
+        self.assertEquals(
+            output.getvalue(),
+            "Found input and output wires with the same name. "
+            "Output 'G3' has now been renamed to 'tmp3'.\n"
+        )
+        pyrtl.working_block().sanity_check()
+
+        self.check_io(pyrtl.Input, ['G1', 'G2', 'G3'])
+        self.check_io(pyrtl.Output, ['tmp3', 'G4'])
+
 
 if __name__ == "__main__":
     unittest.main()