Enable doctest for memory.py.

Author: fdxmw

pyrtl/memory.py

@@ -162,24 +162,31 @@ def __init__(self, bitwidth: int, addrwidth: int, name: str = '',
         ---------------------------
         Simultaneous Read and Write
         ---------------------------
+        ..
+            # For ``doctest``.
+            >>> import pyrtl
+            >>> pyrtl.reset_working_block()
+
         In PyRTL simulations, if the same address is read and written in the same cycle,
         the read will return the `last` value stored in the MemBlock, not the newly
         written value. Example::
 
-            mem = pyrtl.MemBlock(addrwidth=1, bitwidth=1)
-            mem[0] <<= 1
-            read_data = pyrtl.Output(name="read_data", bitwidth=1)
-            read_data <<= mem[0]
+            >>> mem = pyrtl.MemBlock(addrwidth=1, bitwidth=1)
+            >>> mem[0] <<= 1
+            >>> read_data = pyrtl.Output(name="read_data", bitwidth=1)
+            >>> read_data <<= mem[0]
 
-            # In the first cycle, read_data will be the default MemBlock data value (0),
-            # not the newly written value (1).
-            sim = pyrtl.Simulation()
-            sim.step()
-            print("Cycle 0 read_data", sim.inspect("read_data"))
+            >>> # In the first cycle, read_data will be the default MemBlock data value
+            >>> # (0), not the newly written value (1).
+            >>> sim = pyrtl.Simulation()
+            >>> sim.step()
+            >>> sim.inspect("read_data")
+            0
 
             # In the second cycle, read_data will be the newly written value (1).
-            sim.step()
-            print("Cycle 1 read_data", sim.inspect("read_data"))
+            >>> sim.step()
+            >>> sim.inspect("read_data")
+            1
 
         -----------------------------
         Mapping MemBlocks to Hardware

tests/test_memblock.py

@@ -1,10 +1,18 @@
+import doctest
 from random import randint
 import unittest
 
 import pyrtl
 
 
-# -------------------------------------------------------------------
+class TestDocTests(unittest.TestCase):
+    """Test documentation examples."""
+    def test_doctests(self):
+        failures, tests = doctest.testmod(m=pyrtl.memory)
+        self.assertGreater(tests, 0)
+        self.assertEqual(failures, 0)
+
+
 class RTLMemBlockDesignBase(unittest.TestCase):
     def setUp(self):
         pyrtl.reset_working_block()