@@ -410,10 +410,10 @@ def extract_area_delay_from_yosys_output(yosys_output):
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def paths (src = None , dst = None , dst_nets = None , block = None ):
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""" Get the list of paths from src to dst.
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- :param WireVector src: source wire(s) from which to trace your paths;
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- if None, will get paths from all Inputs
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- :param WireVector dst: destination wire(s) to which to trace your paths
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- if None, will get paths to all Outputs
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+ :param Union[ WireVector, Iterable[WireVector]] src: source wire(s) from which to
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+ trace your paths; if None, will get paths from all Inputs
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+ :param Union[ WireVector, Iterable[WireVector]] dst: destination wire(s) to which to
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+ trace your paths; if None, will get paths to all Outputs
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:param {WireVector: {LogicNet}} dst_nets: map from wire to set of nets where the
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wire is an argument; will compute it internally if not given via a
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call to pyrtl.net_connections()
@@ -448,10 +448,21 @@ def paths(src=None, dst=None, dst_nets=None, block=None):
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for output in block .wirevector_subset (cls = Output ):
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dst_nets .pop (output , None )
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- src = block .wirevector_subset (cls = Input ) if src is None else {src }
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- dst = block .wirevector_subset (cls = Output ) if dst is None else {dst }
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+ if src is None :
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+ src = block .wirevector_subset (cls = Input )
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+ elif isinstance (src , WireVector ):
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+ src = {src }
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+ else :
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+ src = set (src )
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+
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+ if dst is None :
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+ dst = block .wirevector_subset (cls = Output )
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+ elif isinstance (dst , WireVector ):
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+ dst = {dst }
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+ else :
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+ dst = set (dst )
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- def paths_src_dst (src , dst , block = None ):
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+ def paths_src_dst (src , dst ):
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paths = []
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# Use DFS to get the paths [each a list of nets] from src wire to dst wire
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