Add tests for the full range of unsigned romblock and memblock values.

Also update pytest configuration to run tests in parallel.

Author: fdxmw

requirements.txt

@@ -3,4 +3,5 @@ pylint
 pyparsing
 pytest
 pytest-cov
+pytest-xdist
 tox

tests/test_compilesim.py

@@ -1009,6 +1009,20 @@ def test_negative_memory_value_map(self):
                                                            bitwidth=mem.bitwidth)
             self.assertEqual(actual_read_data, memory_value_map[i])
 
+    def test_unsigned_memory_value_map(self):
+        mem = pyrtl.MemBlock(addrwidth=3, bitwidth=3)
+        counter = pyrtl.Register(bitwidth=mem.addrwidth)
+        counter.next <<= counter + 1
+        read_data = pyrtl.Output(name="read_data")
+        read_data <<= mem[counter]
+        memory_values = [0, 1, 2, 3, 4, 5, 6, 7]
+        memory_value_map = {index: value for index, value in enumerate(memory_values)}
+        sim = self.sim(memory_value_map={mem: memory_value_map})
+        for i in range(2 ** mem.addrwidth):
+            sim.step()
+            actual_read_data = sim.inspect("read_data")
+            self.assertEqual(actual_read_data, memory_value_map[i])
+
 
 class InspectBase(unittest.TestCase):
     """

tests/test_memblock.py

@@ -399,6 +399,19 @@ def test_negative_romdata(self):
                                                            bitwidth=rom.bitwidth)
             self.assertEqual(actual_read_data, romdata[i])
 
+    def test_unsigned_romdata(self):
+        romdata = [0, 1, 2, 3, 4, 5, 6, 7]
+        rom = pyrtl.RomBlock(addrwidth=3, bitwidth=3, romdata=romdata)
+        counter = pyrtl.Register(bitwidth=rom.addrwidth)
+        counter.next <<= counter + 1
+        read_data = pyrtl.Output(name="read_data", bitwidth=rom.bitwidth)
+        read_data <<= rom[counter]
+        sim = pyrtl.Simulation()
+        for i in range(2 ** rom.addrwidth):
+            sim.step()
+            actual_read_data = sim.inspect("read_data")
+            self.assertEqual(actual_read_data, romdata[i])
+
 
 if __name__ == "__main__":
     unittest.main()

tests/test_simulation.py

@@ -1319,6 +1319,20 @@ def test_negative_memory_value_map(self):
                                                            bitwidth=mem.bitwidth)
             self.assertEqual(actual_read_data, memory_value_map[i])
 
+    def test_unsigned_memory_value_map(self):
+        mem = pyrtl.MemBlock(addrwidth=3, bitwidth=3)
+        counter = pyrtl.Register(bitwidth=mem.addrwidth)
+        counter.next <<= counter + 1
+        read_data = mem[counter]
+        read_data.name = "read_data"
+        memory_values = [0, 1, 2, 3, 4, 5, 6, 7]
+        memory_value_map = {index: value for index, value in enumerate(memory_values)}
+        sim = self.sim(memory_value_map={mem: memory_value_map})
+        for i in range(2 ** mem.addrwidth):
+            sim.step()
+            actual_read_data = sim.inspect("read_data")
+            self.assertEqual(actual_read_data, memory_value_map[i])
+
     def test_simultaneous_read_write(self):
         """Simultaneously read and write address 0.
 

tox.ini

@@ -21,7 +21,7 @@ setenv =
     PYTHONPATH = {toxinidir}
 
 commands =
-    test: pytest --cov=pyrtl --cov-report=xml
+    test: pytest --cov=pyrtl --cov-report=xml -n auto {posargs}
     test: pylint -E pyrtl/
     pycodestyle: pycodestyle --max-line-length=100 --ignore=W503 pyrtl/
     pycodestyle: pycodestyle --max-line-length=100 --ignore=W503 examples/