This will import the Verilog module without making its i/o wires the block's i/o wires. Instead, it returns an object whose attributes are input/output wires, accessible via the name of the wires defined on the Verilog module.

Given this Verilog file

module A(x, y, z);
    parameter in_size = 4;
    parameter out_size = 3;
    input [in_size-1:0] x;
    input y;
    output [out_size-1:0] z;

    assign z = x[2:0] & y;
endmodule
# ... possibly more modules

You can import it like so

with open("sample_verilog.v") as f:
    foo = pyrtl.import_from_verilog(f, toplevel="foo", parameters={'in_size': 8, 'out_size': 5}, as_block=False)

foo.x and foo.y are WireVectors, not Input, and they are named with internal names so the module can be imported multiple times without clashes. Similarly, foo.z is WireVector, not Output. All these wires can be connected to others like normal:

i, j = pyrtl.input_list('i/8 j/5')
foo.x <<= i
foo.y <<= j
pyrtl.probe(foo.z, 'out')

The key is the **as_block** parameter you pass to input_from_verilog, which will determine if block-level I/O is created, or instead a "submodule".

This PR also adds support for importing particular models from a BLIF file (since the input_from_verilog() function basically wraps the call to input_from_blif()).