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Avalon
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‎Avalon/v1/AvalonCommon.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Common types for Avalon Memory-Mapped (MM) interfaces
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--
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-- Description:
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-- Defines shared types for use in Avalon-MM records
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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package AvalonCommon is
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-- Common types
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subtype Data_Type is std_ulogic_vector;
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subtype Address_Type is unsigned;
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subtype ByteEnable_Type is std_ulogic_vector;
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subtype BurstCount_Type is unsigned;
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-- Avalon-MM Response
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subtype Response_Type is std_ulogic_vector(1 downto 0);
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constant AVALON_RESPONSE_OKAY : Response_Type := "00";
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constant AVALON_RESPONSE_RESERVED : Response_Type := "01";
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constant AVALON_RESPONSE_SLAVE_ERROR : Response_Type := "10";
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constant AVALON_RESPONSE_DECODE_ERROR : Response_Type := "11";
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type Avalon_System_Interface is record
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Clock : std_ulogic;
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Reset : std_ulogic;
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end record;
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end package;

‎Avalon/v1/AvalonMM.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- VHDL-2019 Avalon Memory-Mapped (Avalon-MM) interface descriptions
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--
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-- Description:
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-- Signal names match Avalon specification (address, writedata, readdata, etc.)
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.AvalonCommon.all;
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package AvalonMM is
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-- Avalon Memory-Mapped Interface (matching spec signal names)
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type AvalonMM_Interface is record
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-- Master signals
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Address : Address_Type; -- Address
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Read : std_ulogic; -- Read request
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Write : std_ulogic; -- Write request
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WriteData : Data_Type; -- Write data
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ByteEnable : ByteEnable_Type; -- Byte enable
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-- Slave signals
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ReadData : Data_Type; -- Read data
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ReadDataValid : std_ulogic; -- Read data valid
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WaitRequest : std_ulogic; -- Wait request
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Response : Response_Type; -- Response
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-- Optional burst signals
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BurstCount : BurstCount_Type; -- Burst count
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-- Optional pipelining signals
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WriteResponseValid : std_ulogic; -- Write response valid
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-- Optional lock signal
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Lock : std_ulogic; -- Lock
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-- Optional debug signals
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DebugAccess : std_ulogic; -- Debug access
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end record;
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type AvalonMM_Interface_Vector is array(natural range <>) of AvalonMM_Interface;
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-- Master view (from master's perspective)
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view AvalonMM_MasterView of AvalonMM_Interface is
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-- Master outputs
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Address : out;
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Read : out;
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Write : out;
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WriteData : out;
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ByteEnable : out;
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BurstCount : out;
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Lock : out;
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DebugAccess : out;
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-- Master inputs
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ReadData : in;
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ReadDataValid : in;
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WaitRequest : in;
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Response : in;
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WriteResponseValid : in;
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end view;
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alias AvalonMM_SlaveView is AvalonMM_MasterView'converse;
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end package;

‎Avalon/v1/AvalonMM_Generic.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Generic Avalon-MM interface for pre-constraining widths
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--
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-- Description:
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-- Uses spec-matching names (address, writedata, readdata, byteenable, etc.)
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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use work.AvalonMM.all;
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package AvalonMM_Generic is
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generic (
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constant ADDRESS_BITS : positive;
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constant DATA_BITS : positive;
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constant BURSTCOUNT_BITS : positive := 1
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);
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constant BYTEENABLE_BITS : positive := DATA_BITS / 8;
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-- Full Avalon-MM interface with all optional signals
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subtype AvalonMM_SizedInterface is AvalonMM_Interface(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0),
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BurstCount(BURSTCOUNT_BITS - 1 downto 0)
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);
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subtype AvalonMM_SizedInterface_Vector is AvalonMM_Interface_Vector(open)(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0),
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BurstCount(BURSTCOUNT_BITS - 1 downto 0)
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);
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end package;

‎Avalon/v1/AvalonMM_Minimal.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Minimal Avalon Memory-Mapped interface
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--
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-- Description:
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-- Simplified Avalon MM interface without optional signals for basic use cases
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.AvalonCommon.all;
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package AvalonMM_Minimal is
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-- Minimal Avalon MM interface (only essential signals)
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type AvalonMM_Minimal_Interface is record
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-- Master signals
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Address : Address_Type;
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Read : std_ulogic;
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Write : std_ulogic;
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WriteData : Data_Type;
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ByteEnable : ByteEnable_Type;
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-- Slave signals
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ReadData : Data_Type;
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WaitRequest : std_ulogic;
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end record;
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type AvalonMM_Minimal_Interface_Vector is array(natural range <>) of AvalonMM_Minimal_Interface;
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-- Master view
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view AvalonMM_Minimal_MasterView of AvalonMM_Minimal_Interface is
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-- Master outputs
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Address : out;
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Read : out;
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Write : out;
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WriteData : out;
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ByteEnable : out;
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-- Master inputs (slave outputs)
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ReadData : in;
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WaitRequest : in;
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end view;
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alias AvalonMM_Minimal_SlaveView is AvalonMM_Minimal_MasterView'converse;
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end package;

‎Avalon/v1/AvalonMM_Minimal_Generic.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- Generic minimal Avalon Memory-Mapped interface for pre-constraining widths
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--
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-- Description:
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-- Provides sized versions of the minimal Avalon MM interface
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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use work.AvalonMM_Minimal.all;
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package AvalonMM_Minimal_Generic is
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generic (
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constant ADDRESS_BITS : positive;
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constant DATA_BITS : positive
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);
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constant BYTEENABLE_BITS : positive := DATA_BITS / 8;
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-- Sized minimal interface
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subtype AvalonMM_Minimal_SizedInterface is AvalonMM_Minimal_Interface(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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subtype AvalonMM_Minimal_SizedInterface_Vector is AvalonMM_Minimal_Interface_Vector(open)(
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Address(ADDRESS_BITS - 1 downto 0),
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WriteData(DATA_BITS - 1 downto 0),
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ReadData(DATA_BITS - 1 downto 0),
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ByteEnable(BYTEENABLE_BITS - 1 downto 0)
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);
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end package;

‎Avalon/v1/AvalonST.vhdl‎

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-- =============================================================================
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-- Authors:
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-- Parham Soltani
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--
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-- Package:
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-- VHDL-2019 Avalon Streaming (Avalon-ST) interface descriptions
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--
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-- Description:
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-- Signal names match Avalon-ST specification (data, valid, ready, etc.)
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 Open Source VHDL Group
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.AvalonCommon.all;
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package AvalonST is
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-- Avalon Streaming Interface (matching spec signal names)
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type AvalonST_Interface is record
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-- Handshake signals
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Valid : std_ulogic; -- Valid
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Ready : std_ulogic; -- Ready
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-- Payload signals
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Data : Data_Type; -- Data
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-- Packet signals
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StartOfPacket : std_ulogic; -- Start of packet
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EndOfPacket : std_ulogic; -- End of packet
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Empty : std_ulogic_vector; -- Empty (number of empty symbols)
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-- Error signal
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Error : std_ulogic_vector; -- Error
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-- Channel signal
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Channel : std_ulogic_vector; -- Channel
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end record;
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type AvalonST_Interface_Vector is array(natural range <>) of AvalonST_Interface;
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-- Source view (from source's perspective)
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view AvalonST_SourceView of AvalonST_Interface is
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-- Source outputs
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Valid : out;
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Data : out;
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StartOfPacket : out;
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EndOfPacket : out;
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Empty : out;
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Error : out;
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Channel : out;
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-- Source inputs (sink outputs)
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Ready : in;
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end view;
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alias AvalonST_SinkView is AvalonST_SourceView'converse;
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end package;

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