final linebreak added

Author: parhamsoltani

Wishbone/vB3/Wishbone.vhdl

@@ -122,4 +122,4 @@ package Wishbone is
 	end view;
 	alias Wishbone_Simple_SlaveView is Wishbone_Simple_MasterView'converse;
 
-end package;
+end package;

Wishbone/vB3/WishboneCommon.vhdl

@@ -58,4 +58,4 @@ package WishboneCommon is
 		Rst    : std_ulogic;  -- Reset
 	end record;
 
-end package;
+end package;

Wishbone/vB3/Wishbone_Generic.vhdl

@@ -76,4 +76,4 @@ package Wishbone_Generic is
 		Sel(SEL_BITS - 1 downto 0)
 	);
 
-end package;
+end package;