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Feature/wishbone

EnhancementNew feature or requestNew feature or request

InternalMainly internal interface between components.Mainly internal interface between components.

Memory-Mapped

SoC Bus Architecture

Status: Open (in progress).

VHDL/Interfacesnumber 38

#38 In VHDL/Interfaces;

· parhamsoltani opened on Dec 11, 2025

Feature/avalon

EnhancementNew feature or requestNew feature or request

InternalMainly internal interface between components.Mainly internal interface between components.

Memory-Mapped

SoC Bus Architecture

Streaming

Status: Open (in progress).

VHDL/Interfacesnumber 37

#37 In VHDL/Interfaces;

· parhamsoltani opened on Dec 11, 2025