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fix(treewide): Fix virtual/override annotations
Signed-off-by: Philipp Jungkamp <philipp.jungkamp@rwth-aachen.de> Signed-off-by: Steffen Vogel <steffen.vogel@opal-rt.com>
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79 files changed

+276
-274
lines changed

‎clients/shmem/villas-shmem.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ class Shmem : public Tool {
3434
protected:
3535
std::atomic<bool> stop;
3636

37-
void usage() {
37+
void usage() override {
3838
std::cout
3939
<< "Usage: villas-test-shmem WNAME VECTORIZE" << std::endl
4040
<< " WNAME name of the shared memory object for the output queue"
@@ -47,9 +47,9 @@ class Shmem : public Tool {
4747
printCopyright();
4848
}
4949

50-
void handler(int, siginfo_t *, void *) { stop = true; }
50+
void handler(int, siginfo_t *, void *) override { stop = true; }
5151

52-
int main() {
52+
int main() override {
5353
int ret, readcnt, writecnt, avail;
5454

5555
struct ShmemInterface shm;

‎common/include/villas/dsp/window_cosine.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ class CosineWindow : public Window<T> {
2727

2828
T correctionFactor;
2929

30-
virtual T filter(T in, size_type i) const { return in * coefficients[i]; }
30+
T filter(T in, size_type i) const override { return in * coefficients[i]; }
3131

3232
public:
3333
CosineWindow(double a0, double a1, double a2, double a3, double a4,

‎fpga/include/villas/fpga/core.hpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -227,15 +227,15 @@ class CoreFactory : public plugin::Plugin {
227227
// Returns a running and checked FPGA IP
228228
static std::list<std::shared_ptr<Core>> make(Card *card, json_t *json_ips);
229229

230-
virtual std::string getType() const { return "core"; }
230+
std::string getType() const override { return "core"; }
231231

232232
protected:
233233
enum PollingMode {
234234
POLL,
235235
IRQ,
236236
};
237237

238-
Logger getLogger() { return villas::Log::get(getName()); }
238+
Logger getLogger() override { return villas::Log::get(getName()); }
239239

240240
// Configure IP instance from JSON config
241241
virtual void parse(Core &, json_t *) {}
@@ -257,15 +257,15 @@ template <typename T, const char *name, const char *desc, const char *vlnv>
257257
class CorePlugin : public CoreFactory {
258258

259259
public:
260-
virtual std::string getName() const { return name; }
260+
std::string getName() const override { return name; }
261261

262-
virtual std::string getDescription() const { return desc; }
262+
std::string getDescription() const override { return desc; }
263263

264264
private:
265-
virtual Vlnv getCompatibleVlnv() const { return Vlnv(vlnv); }
265+
Vlnv getCompatibleVlnv() const override { return Vlnv(vlnv); }
266266

267267
// Create a concrete IP instance
268-
Core *make() const { return new T; };
268+
Core *make() const override { return new T; };
269269
};
270270

271271
} // namespace ip

‎fpga/include/villas/fpga/ips/aurora.hpp‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,15 +18,17 @@ class Aurora : public Node {
1818
static constexpr const char *masterPort = "m_axis";
1919
static constexpr const char *slavePort = "s_axis";
2020

21-
virtual void dump() override;
21+
void dump() override;
2222

23-
std::list<std::string> getMemoryBlocks() const { return {registerMemory}; }
23+
std::list<std::string> getMemoryBlocks() const override {
24+
return {registerMemory};
25+
}
2426

25-
const StreamVertex &getDefaultSlavePort() const {
27+
const StreamVertex &getDefaultSlavePort() const override {
2628
return getSlavePort(slavePort);
2729
}
2830

29-
const StreamVertex &getDefaultMasterPort() const {
31+
const StreamVertex &getDefaultMasterPort() const override {
3032
return getMasterPort(masterPort);
3133
}
3234

‎fpga/include/villas/fpga/ips/aurora_xilinx.hpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,11 @@ class AuroraXilinx : public Node {
1818
static constexpr const char *masterPort = "USER_DATA_M_AXI_RX";
1919
static constexpr const char *slavePort = "USER_DATA_S_AXI_TX";
2020

21-
const StreamVertex &getDefaultSlavePort() const {
21+
const StreamVertex &getDefaultSlavePort() const override {
2222
return getSlavePort(slavePort);
2323
}
2424

25-
const StreamVertex &getDefaultMasterPort() const {
25+
const StreamVertex &getDefaultMasterPort() const override {
2626
return getMasterPort(masterPort);
2727
}
2828
};

‎fpga/include/villas/fpga/ips/axis_cache.hpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,9 +18,9 @@ namespace ip {
1818
class AxisCache : public Node {
1919
public:
2020
AxisCache();
21-
virtual ~AxisCache();
22-
virtual bool init() override;
23-
virtual bool check() override;
21+
~AxisCache() override;
22+
bool init() override;
23+
bool check() override;
2424
void invalidate();
2525

2626
protected:

‎fpga/include/villas/fpga/ips/bram.hpp‎

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -20,14 +20,16 @@ class Bram : public Core {
2020
friend class BramFactory;
2121

2222
public:
23-
virtual bool init() override;
23+
bool init() override;
2424

2525
LinearAllocator &getAllocator() { return *allocator; }
2626

2727
private:
2828
static constexpr const char *memoryBlock = "Mem0";
2929

30-
std::list<MemoryBlockName> getMemoryBlocks() const { return {memoryBlock}; }
30+
std::list<MemoryBlockName> getMemoryBlocks() const override {
31+
return {memoryBlock};
32+
}
3133

3234
size_t size;
3335
std::unique_ptr<LinearAllocator> allocator;
@@ -36,20 +38,20 @@ class Bram : public Core {
3638
class BramFactory : public CoreFactory {
3739

3840
public:
39-
virtual std::string getName() const { return "bram"; }
41+
std::string getName() const override { return "bram"; }
4042

41-
virtual std::string getDescription() const { return "Block RAM"; }
43+
std::string getDescription() const override { return "Block RAM"; }
4244

4345
private:
44-
virtual Vlnv getCompatibleVlnv() const {
46+
Vlnv getCompatibleVlnv() const override {
4547
return Vlnv("xilinx.com:ip:axi_bram_ctrl:");
4648
}
4749

4850
// Create a concrete IP instance
49-
Core *make() const { return new Bram; };
51+
Core *make() const override { return new Bram; };
5052

5153
protected:
52-
virtual void parse(Core &, json_t *) override;
54+
void parse(Core &, json_t *) override;
5355
};
5456

5557
} // namespace ip

‎fpga/include/villas/fpga/ips/dino.hpp‎

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,8 @@ class Dino : public Node {
5353
enum Gain { GAIN_1 = 0, GAIN_2 = 1, GAIN_5 = 2, GAIN_10 = 3 };
5454

5555
Dino();
56-
virtual ~Dino();
57-
virtual bool init() override;
56+
~Dino() override;
57+
bool init() override;
5858
void setI2c(std::shared_ptr<I2c> i2cdev, uint8_t i2c_channel) {
5959
this->i2cdev = i2cdev;
6060
this->i2c_channel = i2c_channel;
@@ -89,8 +89,8 @@ class Dino : public Node {
8989
class DinoAdc : public Dino {
9090
public:
9191
DinoAdc();
92-
virtual ~DinoAdc();
93-
virtual void configureHardware() override;
92+
~DinoAdc() override;
93+
void configureHardware() override;
9494

9595
/* Set the configuration of the ADC registers
9696
*
@@ -109,42 +109,40 @@ class DinoAdc : public Dino {
109109
class DinoDac : public Dino {
110110
public:
111111
DinoDac();
112-
virtual ~DinoDac();
113-
virtual void configureHardware() override;
112+
~DinoDac() override;
113+
void configureHardware() override;
114114
void setGain(Gain gain);
115115
Gain getGain();
116116
};
117117

118118
class DinoFactory : NodeFactory {
119119
public:
120-
virtual std::string getDescription() const override {
121-
return "Dino Analog I/O";
122-
}
120+
std::string getDescription() const override { return "Dino Analog I/O"; }
123121

124122
protected:
125-
virtual void parse(Core &ip, json_t *json) override;
123+
void parse(Core &ip, json_t *json) override;
126124
};
127125

128126
class DinoAdcFactory : DinoFactory {
129127
public:
130-
virtual std::string getName() const { return "dinoAdc"; }
128+
std::string getName() const override { return "dinoAdc"; }
131129

132130
private:
133-
virtual Vlnv getCompatibleVlnv() const {
131+
Vlnv getCompatibleVlnv() const override {
134132
return Vlnv("xilinx.com:module_ref:dinoif_adc:");
135133
}
136-
Core *make() const { return new DinoAdc; };
134+
Core *make() const override { return new DinoAdc; };
137135
};
138136

139137
class DinoDacFactory : DinoFactory {
140138
public:
141-
virtual std::string getName() const { return "dinoDac"; }
139+
std::string getName() const override { return "dinoDac"; }
142140

143141
private:
144-
virtual Vlnv getCompatibleVlnv() const {
142+
Vlnv getCompatibleVlnv() const override {
145143
return Vlnv("xilinx.com:module_ref:dinoif_dac:");
146144
}
147-
Core *make() const { return new DinoDac; };
145+
Core *make() const override { return new DinoDac; };
148146
};
149147

150148
} // namespace ip

‎fpga/include/villas/fpga/ips/dma.hpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,9 @@ class Dma : public Node {
2525
public:
2626
friend class DmaFactory;
2727

28-
virtual ~Dma();
28+
~Dma() override;
2929

30-
virtual bool init() override;
30+
bool init() override;
3131

3232
bool reset() override;
3333

@@ -84,7 +84,7 @@ class Dma : public Node {
8484
bool isMemoryBlockAccesible(const MemoryBlock &mem,
8585
const std::string &interface);
8686

87-
virtual void dump() override;
87+
void dump() override;
8888

8989
private:
9090
bool writeScatterGather(const void *buf, size_t len);
@@ -154,24 +154,24 @@ class Dma : public Node {
154154
class DmaFactory : NodeFactory {
155155

156156
public:
157-
virtual std::string getName() const override { return "dma"; }
157+
std::string getName() const override { return "dma"; }
158158

159-
virtual std::string getDescription() const override {
159+
std::string getDescription() const override {
160160
return "Xilinx's AXI4 Direct Memory Access Controller";
161161
}
162162

163163
private:
164-
virtual Vlnv getCompatibleVlnv() const override {
164+
Vlnv getCompatibleVlnv() const override {
165165
return Vlnv("xilinx.com:ip:axi_dma:");
166166
}
167167

168168
// Create a concrete IP instance
169169
Core *make() const override { return new Dma; };
170170

171171
protected:
172-
virtual void parse(Core &ip, json_t *json) override;
172+
void parse(Core &ip, json_t *json) override;
173173

174-
virtual void configurePollingMode(Core &ip, PollingMode mode) override {
174+
void configurePollingMode(Core &ip, PollingMode mode) override {
175175
dynamic_cast<Dma &>(ip).polling = (mode == POLL);
176176
}
177177
};

‎fpga/include/villas/fpga/ips/emc.hpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ namespace ip {
1717

1818
class EMC : public Core {
1919
public:
20-
virtual bool init() override;
20+
bool init() override;
2121

2222
bool flash(uint32_t offset, const std::string &filename);
2323
bool flash(uint32_t offset, uint32_t length, uint8_t *data);
@@ -29,7 +29,7 @@ class EMC : public Core {
2929

3030
static constexpr char registerMemory[] = "Reg";
3131

32-
std::list<MemoryBlockName> getMemoryBlocks() const {
32+
std::list<MemoryBlockName> getMemoryBlocks() const override {
3333
return {registerMemory};
3434
}
3535
};

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