- Update synth_preamble.tcl and two_phase_clk_synth.tcl

Author: leeway64

flow/scripts/synth_preamble.tcl

@@ -183,18 +183,19 @@ proc connect_clk {cell_name clock_pin_name target_clk_port_name} {
     }
 }
 
-proc check_logical_equivalence {top_module gold gate} {
+proc check_logical_equivalence {top_module gold gate abc_args lib_args lib_dont_use_args} {
     puts "Save a backup that won't get deleted by this function"
     design -save backup_1
 
     # Create new modules
+    
+    #puts "Create new modules"
     design -copy-from $gold -as gold $top_module
     design -copy-from $gate -as gate $top_module
 
     equiv_make -inames gold gate equiv
-
-    prep -flatten -top equiv
     yosys cd equiv
+    prep -flatten -top equiv
     opt_clean -purge
 
     async2sync

flow/scripts/two_phase_clk_synth.tcl

@@ -87,6 +87,8 @@ delete t:\$print
 # At least this is predictable.
 renames -wire
 
+# Optimize the design
+opt -purge
 
 puts "Duplicate each flip-flop"
 techmap -max_iter 1 -map $::env(DUPLICATE_DFFS_MAP_FILE)
@@ -107,6 +109,7 @@ connect_clk *custom_FF_replace_2.mux_latch C clk_1
 connect_clk *custom_FF_replace_1.mux_latch C clk_2
 
 
+design -save post_retiming
 design -save pre_retiming
 
 puts "Perform retiming"
@@ -116,10 +119,7 @@ opt -noff -purge
 design -save post_retiming
 
 puts "Perform logical equivalence checking"
-check_logical_equivalence $::env(DESIGN_NAME) pre_retiming post_retiming
-
-# Optimize the design
-opt -purge
+check_logical_equivalence $::env(DESIGN_NAME) pre_retiming post_retiming $abc_args $lib_args $lib_dont_use_args
 
 # puts "Replace each DFF with a corresponding latch"
 techmap -autoproc -map $::env(DFF_TO_LATCH_MAP_FILE)