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leeway64leeway64
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‎flow/Makefile‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -258,9 +258,20 @@ $(SDC_FILE_CLOCK_PERIOD): $(SDC_FILE)
258258
.PHONY: yosys-dependencies
259259
yosys-dependencies: $(YOSYS_DEPENDENCIES)
260260

261+
MODE=default
262+
261263
.PHONY: do-yosys
262-
do-yosys: yosys-dependencies
264+
do-yosys: $(DONT_USE_SC_LIB)
265+
ifeq ($(MODE), default)
266+
echo "Running default mode"
263267
$(SCRIPTS_DIR)/synth.sh $(SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log
268+
else ifeq ($(MODE), two_phase_clk)
269+
echo "Running two-phase clocking with latches mode"
270+
$(SCRIPTS_DIR)/synth.sh $(TWO_PHASE_CLK_SYNTH_SCRIPT) $(LOG_DIR)/1_2_yosys.log
271+
else
272+
echo "Mode not recognized. Exiting with error code 1."
273+
exit 1
274+
endif
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265276
.PHONY: do-yosys-canonicalize
266277
do-yosys-canonicalize: yosys-dependencies

‎flow/designs/sky130hd/aes/config.mk‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ export DESIGN_NAME = aes_cipher_top
33
export PLATFORM = sky130hd
44

55
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
6-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
77

88
export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks
99

@@ -20,3 +20,6 @@ export REMOVE_ABC_BUFFERS = 1
2020

2121
export CTS_CLUSTER_SIZE = 20
2222
export CTS_CLUSTER_DIAMETER = 50
23+
24+
# This allows Yosys to print more details to the terminal during execution
25+
export YOSYS_FLAGS

flow/designs/sky130hd/aes/constraint.sdc renamed to flow/designs/sky130hd/aes/default_constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design aes_cipher_top
22

33
set clk_name clk
44
set clk_port_name clk
5-
set clk_period 4.5
5+
set clk_period [expr 1 * 4.5]
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/sky130hd/aes/two_phase_clk_constraint.sdc‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
############### Preliminaries ###############
2+
3+
current_design aes_cipher_top
4+
5+
set clk_period [expr 1 * 4.5]
6+
set clk_io_pct 0.2
7+
set duty_cycle 0.4
8+
9+
set clk_1_rise 0.0
10+
set clk_1_fall [expr {$clk_period * $duty_cycle}]
11+
set clk_2_rise [expr {$clk_period / 2}]
12+
set clk_2_fall [expr ($clk_period / 2) + ($clk_period * $duty_cycle)]
13+
14+
set clk_1_waveform_list {}
15+
lappend clk_1_waveform_list $clk_1_rise
16+
lappend clk_1_waveform_list $clk_1_fall
17+
18+
set clk_2_waveform_list {}
19+
lappend clk_2_waveform_list $clk_2_rise
20+
lappend clk_2_waveform_list $clk_2_fall
21+
22+
23+
############### Set up default clock ###############
24+
25+
set default_clk_name default_clk
26+
27+
create_clock -name $default_clk_name -period $clk_period
28+
29+
30+
############### Set up clock 1 ###############
31+
32+
set clk_1_name clk_1
33+
set clk_1_port_name clk_1
34+
35+
set clk_1_port [get_ports $clk_1_port_name]
36+
37+
create_clock -name $clk_1_name -period $clk_period $clk_1_port -waveform $clk_1_waveform_list
38+
39+
40+
############### Set up clock 2 ###############
41+
42+
set clk_2_name clk_2
43+
set clk_2_port_name clk_2
44+
45+
set clk_2_port [get_ports $clk_2_port_name]
46+
47+
create_clock -name $clk_2_name -period $clk_period $clk_2_port -waveform $clk_2_waveform_list
48+
49+
50+
############### Create non-clock inputs ###############
51+
52+
set non_clock_inputs [all_inputs -no_clocks]
53+
54+
55+
############### Set input and output delays ###############
56+
57+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name $non_clock_inputs
58+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name [all_outputs]
59+
60+
61+
############### Set up constraints for setup and hold checks ###############
62+
63+
set_multicycle_path 2 -setup -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
64+
set_multicycle_path 2 -setup -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]
65+
66+
set_multicycle_path 1 -hold -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
67+
set_multicycle_path 1 -hold -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]

‎flow/designs/sky130hd/gcd/config.mk‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ export DESIGN_NAME = gcd
22
export PLATFORM = sky130hd
33

44
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v
5-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
5+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
66

77
# Adders degrade GCD
88
export ADDER_MAP_FILE :=
@@ -11,3 +11,6 @@ export CORE_UTILIZATION = 40
1111
export TNS_END_PERCENT = 100
1212
export EQUIVALENCE_CHECK ?= 1
1313
export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd__tapvpwrvgnd*
14+
15+
# This allows Yosys to print more details to the terminal during execution
16+
export YOSYS_FLAGS

flow/designs/sky130hd/gcd/constraint.sdc renamed to flow/designs/sky130hd/gcd/default_constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design gcd
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 1.1
5+
set clk_period [expr 3 * 1.1]
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/sky130hd/gcd/two_phase_clk_constraint.sdc‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
############### Preliminaries ###############
2+
3+
current_design gcd
4+
5+
set clk_period [expr 3 * 1.1]
6+
set clk_io_pct 0.2
7+
set duty_cycle 0.4
8+
9+
set clk_1_rise 0.0
10+
set clk_1_fall [expr {$clk_period * $duty_cycle}]
11+
set clk_2_rise [expr {$clk_period / 2}]
12+
set clk_2_fall [expr ($clk_period / 2) + ($clk_period * $duty_cycle)]
13+
14+
set clk_1_waveform_list {}
15+
lappend clk_1_waveform_list $clk_1_rise
16+
lappend clk_1_waveform_list $clk_1_fall
17+
18+
set clk_2_waveform_list {}
19+
lappend clk_2_waveform_list $clk_2_rise
20+
lappend clk_2_waveform_list $clk_2_fall
21+
22+
23+
############### Set up default clock ###############
24+
25+
set default_clk_name default_clk
26+
27+
create_clock -name $default_clk_name -period $clk_period
28+
29+
30+
############### Set up clock 1 ###############
31+
32+
set clk_1_name clk_1
33+
set clk_1_port_name clk_1
34+
35+
set clk_1_port [get_ports $clk_1_port_name]
36+
37+
create_clock -name $clk_1_name -period $clk_period $clk_1_port -waveform $clk_1_waveform_list
38+
39+
40+
############### Set up clock 2 ###############
41+
42+
set clk_2_name clk_2
43+
set clk_2_port_name clk_2
44+
45+
set clk_2_port [get_ports $clk_2_port_name]
46+
47+
create_clock -name $clk_2_name -period $clk_period $clk_2_port -waveform $clk_2_waveform_list
48+
49+
50+
############### Create non-clock inputs ###############
51+
52+
set non_clock_inputs [all_inputs -no_clocks]
53+
54+
55+
############### Set input and output delays ###############
56+
57+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name $non_clock_inputs
58+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name [all_outputs]
59+
60+
61+
############### Set up constraints for setup and hold checks ###############
62+
63+
set_multicycle_path 2 -setup -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
64+
set_multicycle_path 2 -setup -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]
65+
66+
set_multicycle_path 1 -hold -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
67+
set_multicycle_path 1 -hold -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]

‎flow/designs/sky130hd/riscv32i/config.mk‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,12 @@ export DESIGN_NAME = riscv
33
export PLATFORM = sky130hd
44

55
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
6-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
77

88
export CORE_UTILIZATION = 45
99
export PLACE_DENSITY_LB_ADDON = 0.2
1010

1111
export REMOVE_ABC_BUFFERS = 1
12+
13+
# This allows Yosys to print more details to the terminal during execution
14+
export YOSYS_FLAGS

flow/designs/sky130hd/riscv32i/constraint.sdc renamed to flow/designs/sky130hd/riscv32i/default_constraint.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name clk
22
set clk_port_name clk
3-
set clk_period 6.0
3+
set clk_period [expr 3 * 6.0]
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]

‎flow/designs/sky130hd/riscv32i/two_phase_clk_constraint.sdc‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
############### Preliminaries ###############
2+
3+
current_design riscv
4+
5+
set clk_period [expr 3 * 6.0]
6+
set clk_io_pct 0.2
7+
set duty_cycle 0.4
8+
9+
set clk_1_rise 0.0
10+
set clk_1_fall [expr {$clk_period * $duty_cycle}]
11+
set clk_2_rise [expr {$clk_period / 2}]
12+
set clk_2_fall [expr ($clk_period / 2) + ($clk_period * $duty_cycle)]
13+
14+
set clk_1_waveform_list {}
15+
lappend clk_1_waveform_list $clk_1_rise
16+
lappend clk_1_waveform_list $clk_1_fall
17+
18+
set clk_2_waveform_list {}
19+
lappend clk_2_waveform_list $clk_2_rise
20+
lappend clk_2_waveform_list $clk_2_fall
21+
22+
23+
############### Set up default clock ###############
24+
25+
set default_clk_name default_clk
26+
27+
create_clock -name $default_clk_name -period $clk_period
28+
29+
30+
############### Set up clock 1 ###############
31+
32+
set clk_1_name clk_1
33+
set clk_1_port_name clk_1
34+
35+
set clk_1_port [get_ports $clk_1_port_name]
36+
37+
create_clock -name $clk_1_name -period $clk_period $clk_1_port -waveform $clk_1_waveform_list
38+
39+
40+
############### Set up clock 2 ###############
41+
42+
set clk_2_name clk_2
43+
set clk_2_port_name clk_2
44+
45+
set clk_2_port [get_ports $clk_2_port_name]
46+
47+
create_clock -name $clk_2_name -period $clk_period $clk_2_port -waveform $clk_2_waveform_list
48+
49+
50+
############### Create non-clock inputs ###############
51+
52+
set non_clock_inputs [all_inputs -no_clocks]
53+
54+
55+
############### Set input and output delays ###############
56+
57+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name $non_clock_inputs
58+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $default_clk_name [all_outputs]
59+
60+
61+
############### Set up constraints for setup and hold checks ###############
62+
63+
set_multicycle_path 2 -setup -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
64+
set_multicycle_path 2 -setup -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]
65+
66+
set_multicycle_path 1 -hold -from [get_clocks $default_clk_name] -to [get_clocks $clk_1_name]
67+
set_multicycle_path 1 -hold -from [get_clocks $clk_2_name] -to [get_clocks $default_clk_name]

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