Skip to content

Commit acb32dc

Browse files
committed
Create ABC_RETIME_FOR_TWO_PHASE variable in config.mk files for aes, gcd, and riscv32i
1 parent ba41345 commit acb32dc

File tree

3 files changed

+6
-0
lines changed

3 files changed

+6
-0
lines changed

flow/designs/sky130hd/aes/config.mk

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@ export PLATFORM = sky130hd
55
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
66
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
77

8+
export ABC_RETIME_FOR_TWO_PHASE = 1
9+
810
export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks
911

1012
export CORE_UTILIZATION = 20

flow/designs/sky130hd/gcd/config.mk

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@ export PLATFORM = sky130hd
44
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/gcd.v
55
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
66

7+
export ABC_RETIME_FOR_TWO_PHASE = 1
8+
79
# Adders degrade GCD
810
export ADDER_MAP_FILE :=
911

flow/designs/sky130hd/riscv32i/config.mk

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@ export PLATFORM = sky130hd
55
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
66
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/two_phase_clk_constraint.sdc
77

8+
export ABC_RETIME_FOR_TWO_PHASE = 1
9+
810
export CORE_UTILIZATION = 45
911
export PLACE_DENSITY_LB_ADDON = 0.2
1012

0 commit comments

Comments
 (0)