|
1 | | -# Spice |
| 1 | +# SPICE |
2 | 2 |
|
3 | | -Spice is an industry standard circuit file format. It is a textual schematic |
| 3 | +SPICE is an industry standard circuit file format. It is a textual schematic |
4 | 4 | representation of a circuit. It is used by many circuit simulators to simulate |
5 | 5 | the circuit. |
6 | 6 |
|
7 | | -## Spice netlsits |
| 7 | +SPICE files are text files and can be edited with any text editor. Suffixes for |
| 8 | +SPICE files can have many variations including: |
| 9 | +- .sp |
| 10 | +- .spi |
| 11 | +- .spice |
| 12 | +- .cdl |
| 13 | +- .cir |
| 14 | +- .ckt |
| 15 | +- probably others too |
| 16 | + |
| 17 | +## How are SPICE netlists created |
| 18 | + |
| 19 | +SPICE netlists can be created in a number of ways: |
| 20 | + |
| 21 | +1. By hand: You can write a SPICE netlist by hand. This is often done for simple |
| 22 | + circuits or for testing a simulator. |
| 23 | +2. By exporting from a schematic capture tool: Many schematic capture tools can |
| 24 | + export a SPICE netlist. This is often done for more complex circuits. |
| 25 | +3. Layout extraction: Layout extraction tools can extract a SPICE netlist from a |
| 26 | + layout. |
| 27 | + |
| 28 | +Standard cell libraries will often come with SPICE netlists for the cells. Sometimes |
| 29 | +these will be individual files, or sometimes they might all be in a single large file. |
| 30 | +The Sky130 library has its cells in: |
| 31 | +``` |
| 32 | +$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice |
| 33 | +``` |
| 34 | +There are also CDL versions in: |
| 35 | +``` |
| 36 | +$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl |
| 37 | +``` |
| 38 | + |
| 39 | + |
| 40 | +## SPICE syntax |
| 41 | + |
| 42 | +It's easiest to talk about SPICE netlists with an example. Here's the spice |
| 43 | +netlist (actually, a CDL netlist) of an inverter: |
| 44 | +``` |
| 45 | +* Inverter example |
| 46 | +.SUBCKT sky130_fd_sc_hd__inv_1 A VGND VNB VPB VPWR Y |
| 47 | +*.PININFO A:I VGND:I VNB:I VPB:I VPWR:I Y:O |
| 48 | +MMIN1 Y A VGND VNB sky130_fd_pr__nfet_01v8 m=1 w=0.65u l=0.15u mult=1 sa=0.265 |
| 49 | ++ sb=0.265 sd=0.28 area=0.063 perim=1.14 |
| 50 | +MMIP1 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt m=1 w=1.1u l=0.15u mult=1 sa=0.265 |
| 51 | ++ sb=0.265 sd=0.28 area=0.063 perim=1.14 |
| 52 | +.ENDS sky130_fd_sc_hd__inv_1 |
| 53 | +``` |
| 54 | + |
| 55 | +*The first line of a SPICE file is always ignored!* In this case, it is a comment. |
| 56 | + |
| 57 | +### Subcircuits |
| 58 | + |
| 59 | +Subcircuits are specified with the .SUBCKT/.ENDS pair. In this case, the second |
| 60 | +line says that the subcircuit is named `sky130_fd_sc_hd__inv_1` and has the |
| 61 | +following pins: A, VGND, VNB, VPB, VPWR, and Y. In general, SPICE is case insensitive, |
| 62 | +but it is good practice to use all caps for the subcircuit pins. |
| 63 | + |
| 64 | +The third line is technically a comment, but it is a special comment called a |
| 65 | +pragma that tells a tool about the types of pins. By default, pins have no |
| 66 | +direction in SPICE, but CDL (Cadence Design Language) netlists can have |
| 67 | +directions: I for input and O for output. This pragma is ignored by SPICE |
| 68 | +simulators that don't understand it. |
| 69 | + |
| 70 | +### Cards |
| 71 | + |
| 72 | +Every line in a SPICE file is a "card" that describes a device. The first character of |
| 73 | +the first word defines the device type: M for a MOSFET, R for a resistor, C for a capacitor, etc. |
| 74 | + |
| 75 | +A transistor card looks like this: |
| 76 | +``` |
| 77 | +<instance name> <drain> <gate> <source> <bulk> <model name> <parameters> |
| 78 | +``` |
| 79 | +The instance must be unique or you will get an error. The drain, gate, source, and bulk |
| 80 | +are the connections to the transistor. The model name is the name of the model in the |
| 81 | +library. |
| 82 | + |
| 83 | +The parameters for a transistor are specific to the model, but they always include width (W) and length (L) for a MOSFET. |
| 84 | +The parameter M is the number of transistors in parallel. |
| 85 | + |
| 86 | +Resistor and capacitor cards are similar: |
| 87 | +``` |
| 88 | +<instance name> <node 1> <node 2> <value> |
| 89 | +``` |
| 90 | +where an instance name starting with R is a resistor and an instance name starting with C is a capacitor. |
| 91 | +The value is the resistance or capacitance in ohms or farads, respectively. |
| 92 | + |
| 93 | + |
| 94 | +Devices are connected to nets (or nodes) in SPICE which define what is connected together. |
| 95 | +All of the SUBCKT pins are nets, but you can also have other internal nets as well. |
| 96 | +Ground is always node (or net) 0 in SPICE. In "old school" SPICE, nets were often just numbers, |
| 97 | +but it is easier to give them names. |
| 98 | + |
| 99 | +### Instances |
| 100 | + |
| 101 | +Instances are special SPICE cards that being with an X. They are used to instantiate |
| 102 | +subcircuit copies like this: |
| 103 | +``` |
| 104 | +X0 in 0 vdd 0 vdd out sky130_fd_sc_hd__inv_1 |
| 105 | +``` |
| 106 | +which creates an instance of the `sky130_fd_sc_hd__inv_1` subcircuit with the |
| 107 | +name `X0`. The connections to this instance are in the order of the SUBCKT |
| 108 | +definition at the start of this tutorial. Inside the SUBCKT, they have the name |
| 109 | +of the SUBCKT pins, and outside they have these names. The VPWR and VNB pins are both |
| 110 | +connected externally to the vdd net. The VGND and VPB pins are both connected to the 0 net. |
| 111 | + |
| 112 | +### SPICE hierarchy and scope |
| 113 | + |
| 114 | +You can declare instances in a SUBCKT. For example, I can make a BUFFER subcircuit from the inverter like this: |
| 115 | +``` |
| 116 | +.SUBCKT BUFFER IN VDD GND OUT |
| 117 | +X0 IN 0 VDD 0 VDD n10 sky130_fd_sc_hd__inv_1 |
| 118 | +X1 n10 0 VDD 0 VDD OUT sky130_fd_sc_hd__inv_1 |
| 119 | +.ENDS BUFFER |
| 120 | +``` |
| 121 | +SPICE has only one level of scope for SUBCKTs. This means you cannot have duplicate names. If you repeat names, |
| 122 | +most often it will silently overwrite the previous definition. |
| 123 | + |
| 124 | +The scope inside of each SUBCKT is separate from the global scope. |
| 125 | + |
| 126 | +Given the above buffer SUBCKT, I can declare an instance of the buffer like this: |
| 127 | +``` |
| 128 | +X2 bufin vdd 0 bufout BUFFER |
| 129 | +``` |
| 130 | +You can refer to nets in a SUBCKT from the global scope, but you cannot refer to nets in the global scope from a SUBCKT. |
| 131 | +For example, if you have an instance X2 of the BUFFER, I can refer to `X2.n10` which is the signal between the two inverters. |
| 132 | +Similarly, `X2.X0.A` is the input of the first inverter in the buffer. At the top level, it is called "bufin". Inside the BUFFER, |
| 133 | +it is called `X2.IN`. |
| 134 | + |
| 135 | +## Simulating SPICE |
| 136 | + |
| 137 | +To simulate SPICE, you need a stimulus file as well as a netlist file. These can be in the |
| 138 | +same file, but often they are kept separate. The stimulus file will often use the .INCLUDE |
| 139 | +directive to include the netlist file. If the netlist file has a subcircuit, the stimulus |
| 140 | +file may also create an instance of it. |
| 141 | + |
| 142 | +Here is an example of a stimulus file for the inverter above (again, the first line is ignored!): |
| 143 | +``` |
| 144 | +* Inverter testbench |
| 145 | +.INCLUDE BUFFER.spice |
| 146 | +.TRAN 1n 10n |
| 147 | +Vdd vdd 0 1.8 |
| 148 | +
|
| 149 | +X2 bufin vdd 0 bufout BUFFER |
| 150 | +
|
| 151 | +Vinput bufin 0 PULSE(0 1.8 0 0.1n 0.1n 1n 2n) |
| 152 | +
|
| 153 | +.MEASURE tran_delay TRIG v(bufin)*0.5 RISE=1 TARG v(bufout)*0.5 RISE=1 |
| 154 | +``` |
8 | 155 |
|
9 | | -## Spice stimulus |
10 | 156 |
|
11 | | -## Simulating spice |
12 | 157 |
|
0 commit comments