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| 1 | +<?xml version="1.0" encoding="utf-8"?> |
| 2 | +<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd"> |
| 3 | + <key id="BA" for="node" attr.name="base_addr" attr.type="string"/> |
| 4 | + <key id="BP" for="node" attr.name="base_param" attr.type="string"/> |
| 5 | + <key id="EH" for="edge" attr.name="edge_hid" attr.type="int"/> |
| 6 | + <key id="HA" for="node" attr.name="high_addr" attr.type="string"/> |
| 7 | + <key id="HP" for="node" attr.name="high_param" attr.type="string"/> |
| 8 | + <key id="LT" for="node" attr.name="lock_type" attr.type="string"/> |
| 9 | + <key id="MA" for="node" attr.name="master_addrspace" attr.type="string"/> |
| 10 | + <key id="MX" for="node" attr.name="master_instance" attr.type="string"/> |
| 11 | + <key id="MI" for="node" attr.name="master_interface" attr.type="string"/> |
| 12 | + <key id="MS" for="node" attr.name="master_segment" attr.type="string"/> |
| 13 | + <key id="MV" for="node" attr.name="master_vlnv" attr.type="string"/> |
| 14 | + <key id="TM" for="node" attr.name="memory_type" attr.type="string"/> |
| 15 | + <key id="SX" for="node" attr.name="slave_instance" attr.type="string"/> |
| 16 | + <key id="SI" for="node" attr.name="slave_interface" attr.type="string"/> |
| 17 | + <key id="MM" for="node" attr.name="slave_memmap" attr.type="string"/> |
| 18 | + <key id="SS" for="node" attr.name="slave_segment" attr.type="string"/> |
| 19 | + <key id="SV" for="node" attr.name="slave_vlnv" attr.type="string"/> |
| 20 | + <key id="TU" for="node" attr.name="usage_type" attr.type="string"/> |
| 21 | + <key id="VH" for="node" attr.name="vert_hid" attr.type="int"/> |
| 22 | + <key id="VM" for="node" attr.name="vert_name" attr.type="string"/> |
| 23 | + <key id="VT" for="node" attr.name="vert_type" attr.type="string"/> |
| 24 | + <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst"> |
| 25 | + <node id="n0"> |
| 26 | + <data key="BA">0x40400000</data> |
| 27 | + <data key="BP">C_BASEADDR</data> |
| 28 | + <data key="HA">0x4040FFFF</data> |
| 29 | + <data key="HP">C_HIGHADDR</data> |
| 30 | + <data key="MA">Data</data> |
| 31 | + <data key="MX">/processing_system7_0</data> |
| 32 | + <data key="MI">M_AXI_GP0</data> |
| 33 | + <data key="MS">SEG_axi_dma_0_Reg</data> |
| 34 | + <data key="MV">xilinx.com:ip:processing_system7:5.5</data> |
| 35 | + <data key="TM">both</data> |
| 36 | + <data key="SX">/axi_dma_0</data> |
| 37 | + <data key="SI">S_AXI_LITE</data> |
| 38 | + <data key="SS">Reg</data> |
| 39 | + <data key="SV">xilinx.com:ip:axi_dma:7.1</data> |
| 40 | + <data key="TU">register</data> |
| 41 | + <data key="VT">AC</data> |
| 42 | + </node> |
| 43 | + <node id="n1"> |
| 44 | + <data key="BA">0x00000000</data> |
| 45 | + <data key="BP">C_BASEADDR</data> |
| 46 | + <data key="HA">0x1FFFFFFF</data> |
| 47 | + <data key="HP">C_HIGHADDR</data> |
| 48 | + <data key="MA">Data_MM2S</data> |
| 49 | + <data key="MX">/axi_dma_0</data> |
| 50 | + <data key="MI">M_AXI_MM2S</data> |
| 51 | + <data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data> |
| 52 | + <data key="MV">xilinx.com:ip:axi_dma:7.1</data> |
| 53 | + <data key="TM">both</data> |
| 54 | + <data key="SX">/processing_system7_0</data> |
| 55 | + <data key="SI">S_AXI_HP0</data> |
| 56 | + <data key="SS">HP0_DDR_LOWOCM</data> |
| 57 | + <data key="SV">xilinx.com:ip:processing_system7:5.5</data> |
| 58 | + <data key="TU">memory</data> |
| 59 | + <data key="VT">AC</data> |
| 60 | + </node> |
| 61 | + <node id="n2"> |
| 62 | + <data key="TU">active</data> |
| 63 | + <data key="VH">2</data> |
| 64 | + <data key="VT">PM</data> |
| 65 | + </node> |
| 66 | + <node id="n3"> |
| 67 | + <data key="BA">0x00000000</data> |
| 68 | + <data key="BP">C_BASEADDR</data> |
| 69 | + <data key="HA">0x1FFFFFFF</data> |
| 70 | + <data key="HP">C_HIGHADDR</data> |
| 71 | + <data key="MA">Data_S2MM</data> |
| 72 | + <data key="MX">/axi_dma_0</data> |
| 73 | + <data key="MI">M_AXI_S2MM</data> |
| 74 | + <data key="MS">SEG_processing_system7_0_HP0_DDR_LOWOCM</data> |
| 75 | + <data key="MV">xilinx.com:ip:axi_dma:7.1</data> |
| 76 | + <data key="TM">both</data> |
| 77 | + <data key="SX">/processing_system7_0</data> |
| 78 | + <data key="SI">S_AXI_HP0</data> |
| 79 | + <data key="SS">HP0_DDR_LOWOCM</data> |
| 80 | + <data key="SV">xilinx.com:ip:processing_system7:5.5</data> |
| 81 | + <data key="TU">memory</data> |
| 82 | + <data key="VT">AC</data> |
| 83 | + </node> |
| 84 | + <node id="n4"> |
| 85 | + <data key="VH">2</data> |
| 86 | + <data key="VM">dmaSystem</data> |
| 87 | + <data key="VT">VR</data> |
| 88 | + </node> |
| 89 | + <node id="n5"> |
| 90 | + <data key="VM">dmaSystem</data> |
| 91 | + <data key="VT">BC</data> |
| 92 | + </node> |
| 93 | + <edge id="e0" source="n5" target="n4"/> |
| 94 | + <edge id="e1" source="n4" target="n2"/> |
| 95 | + <edge id="e2" source="n0" target="n2"> |
| 96 | + <data key="EH">2</data> |
| 97 | + </edge> |
| 98 | + <edge id="e3" source="n1" target="n2"> |
| 99 | + <data key="EH">2</data> |
| 100 | + </edge> |
| 101 | + <edge id="e4" source="n3" target="n2"> |
| 102 | + <data key="EH">2</data> |
| 103 | + </edge> |
| 104 | + </graph> |
| 105 | +</graphml> |
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