Validate generated Verilog code with Verilator

[VMois]

Verilator is a famous open-source tool for Verilog simulations. Before trying to run the project on a FPGA board, it would be great to verify that our generated verilog code is correct.

chiseltest library has support for Verilator backend - https://github.com/ucb-bar/chiseltest. I assume it will probably generate a Verilog and feed it into Verilator but it needs to be checked. We want to be sure that generated Verilog is correct.