diff --git a/.gitignore b/.gitignore index 3eddf1f..c864968 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,12 @@ generated/ test_run_dir/* +### Xilinx Vivado files, custom for LSM-Compactron3000 +*.gen/ +*.hw/ +*.cache/ +*.ip_user_files/ + ### XilinxISE template # intermediate build files *.bgn diff --git a/README.md b/README.md index aedf819..58c9f0f 100644 --- a/README.md +++ b/README.md @@ -81,6 +81,21 @@ The proposed memory sizes are described in the table below. - [Collection of different useful small Chisel3 projects](https://github.com/j-marjanovic/chisel-stuff) - [Project that shows how Chisel and Rust can have a custom peripherals](https://github.com/ekiwi/pynq) +- https://github.com/alexforencich/verilog-axi - verilog axi interfaces + +- https://github.com/ZipCPU/wb2axip - AXI4, Wishbobe and other interfaces + +### Zynq DMA tutorials + +- https://www.youtube.com/watch?v=tQpt2N7__NQ +- https://www.youtube.com/watch?v=5gA3xnsSrdo +- https://www.youtube.com/watch?v=Ld01yPmW_Xw +- https://www.youtube.com/watch?v=5MCkjKhn1DM + +### Others + +- [Version control for Vivado](https://www.fpgadeveloper.com/2014/08/version-control-for-vivado-projects.html/) + ## Development ### Create Docker Image diff --git a/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bd b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bd new file mode 100644 index 0000000..f8aa649 --- /dev/null +++ b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bd @@ -0,0 +1,2235 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0xCC6CFA539DDF0AAD", + "device": "xc7z010clg400-1", + "gen_directory": "../../../../LSM-Compactron3000.gen/sources_1/bd/dmaSuperSystem", + "name": "dmaSuperSystem", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2022.1" + }, + "design_tree": { + "processing_system7_0": "", + "axi_dma_0": "", + "ps7_0_axi_periph": { + "s00_couplers": { + "auto_pc": "" + } + }, + "rst_ps7_0_100M": "", + "axi_mem_intercon": { + "xbar": "", + "s00_couplers": { + "auto_us": "" + }, + "s01_couplers": { + "auto_us": "" + }, + "m00_couplers": { + "auto_pc": "" + } + }, + "system_ila_0": "", + "DummyKvPairFifo_0": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0" + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0" + } + }, + "components": { + "processing_system7_0": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "xci_name": "dmaSuperSystem_processing_system7_0_0", + "xci_path": "ip\\dmaSuperSystem_processing_system7_0_0\\dmaSuperSystem_processing_system7_0_0.xci", + "inst_hier_path": "processing_system7_0", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "650.000000" + }, + "PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": { + "value": "23.8095" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.096154" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_I2C_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_USB0_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_USB1_PERIPHERAL_FREQMHZ": { + "value": "60" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "108.333336" + }, + "PCW_APU_CLK_RATIO_ENABLE": { + "value": "6:2:1" + }, + "PCW_APU_PERIPHERAL_FREQMHZ": { + "value": "650" + }, + "PCW_CAN0_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN1_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_CAN1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_CAN_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_CAN_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "10000000" + }, + "PCW_CLK2_FREQ": { + "value": "10000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_CPU_CPU_6X4X_MAX_RANGE": { + "value": "667" + }, + "PCW_CPU_PERIPHERAL_CLKSRC": { + "value": "ARM PLL" + }, + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_DCI_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.159" + }, + "PCW_DDR_PERIPHERAL_CLKSRC": { + "value": "DDR PLL" + }, + "PCW_DDR_RAM_BASEADDR": { + "value": "0x00100000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x1FFFFFFF" + }, + "PCW_DM_WIDTH": { + "value": "4" + }, + "PCW_DQS_WIDTH": { + "value": "4" + }, + "PCW_DQ_WIDTH": { + "value": "32" + }, + "PCW_ENET0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_ENET1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_ENET_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_EN_4K_TIMER": { + "value": "0" + }, + "PCW_EN_CAN0": { + "value": "0" + }, + "PCW_EN_CAN1": { + "value": "0" + }, + "PCW_EN_CLK0_PORT": { + "value": "1" + }, + "PCW_EN_CLK1_PORT": { + "value": "0" + }, + "PCW_EN_CLK2_PORT": { + "value": "0" + }, + "PCW_EN_CLK3_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG0_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG1_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG2_PORT": { + "value": "0" + }, + "PCW_EN_CLKTRIG3_PORT": { + "value": "0" + }, + "PCW_EN_DDR": { + "value": "1" + }, + "PCW_EN_EMIO_CAN0": { + "value": "0" + }, + "PCW_EN_EMIO_CAN1": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_CD_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_ENET0": { + "value": "0" + }, + "PCW_EN_EMIO_ENET1": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "0" + }, + "PCW_EN_EMIO_I2C0": { + "value": "0" + }, + "PCW_EN_EMIO_I2C1": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_PJTAG": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_SPI1": { + "value": "0" + }, + "PCW_EN_EMIO_SRAM_INT": { + "value": "0" + }, + "PCW_EN_EMIO_TRACE": { + "value": "0" + }, + "PCW_EN_EMIO_TTC0": { + "value": "0" + }, + "PCW_EN_EMIO_TTC1": { + "value": "0" + }, + "PCW_EN_EMIO_UART0": { + "value": "0" + }, + "PCW_EN_EMIO_UART1": { + "value": "0" + }, + "PCW_EN_EMIO_WDT": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO1": { + "value": "0" + }, + "PCW_EN_ENET0": { + "value": "0" + }, + "PCW_EN_ENET1": { + "value": "0" + }, + "PCW_EN_GPIO": { + "value": "0" + }, + "PCW_EN_I2C0": { + "value": "0" + }, + "PCW_EN_I2C1": { + "value": "0" + }, + "PCW_EN_MODEM_UART0": { + "value": "0" + }, + "PCW_EN_MODEM_UART1": { + "value": "0" + }, + "PCW_EN_PJTAG": { + "value": "0" + }, + "PCW_EN_PTP_ENET0": { + "value": "0" + }, + "PCW_EN_PTP_ENET1": { + "value": "0" + }, + "PCW_EN_QSPI": { + "value": "0" + }, + "PCW_EN_RST0_PORT": { + "value": "1" + }, + "PCW_EN_RST1_PORT": { + "value": "0" + }, + "PCW_EN_RST2_PORT": { + "value": "0" + }, + "PCW_EN_RST3_PORT": { + "value": "0" + }, + "PCW_EN_SDIO0": { + "value": "0" + }, + "PCW_EN_SDIO1": { + "value": "0" + }, + "PCW_EN_SMC": { + "value": "0" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_EN_SPI1": { + "value": "0" + }, + "PCW_EN_TRACE": { + "value": "0" + }, + "PCW_EN_TTC0": { + "value": "0" + }, + "PCW_EN_TTC1": { + "value": "0" + }, + "PCW_EN_UART0": { + "value": "0" + }, + "PCW_EN_UART1": { + "value": "1" + }, + "PCW_EN_USB0": { + "value": "0" + }, + "PCW_EN_USB1": { + "value": "0" + }, + "PCW_EN_WDT": { + "value": "0" + }, + "PCW_FCLK0_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK1_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK2_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK3_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_FCLK_CLK0_BUF": { + "value": "TRUE" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "50" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_GP0_EN_MODIFIABLE_TXN": { + "value": "1" + }, + "PCW_GP0_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP0_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GP1_EN_MODIFIABLE_TXN": { + "value": "1" + }, + "PCW_GP1_NUM_READ_THREADS": { + "value": "4" + }, + "PCW_GP1_NUM_WRITE_THREADS": { + "value": "4" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_MIO_GPIO_ENABLE": { + "value": "0" + }, + "PCW_GPIO_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_I2C_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_IMPORT_BOARD_PRESET": { + "value": "None" + }, + "PCW_INCLUDE_ACP_TRANS_CHECK": { + "value": "0" + }, + "PCW_MIO_48_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_48_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_48_SLEW": { + "value": "slow" + }, + "PCW_MIO_49_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_49_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_49_SLEW": { + "value": "slow" + }, + "PCW_MIO_PRIMITIVE": { + "value": "54" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": { + "value": "0" + }, + "PCW_M_AXI_GP0_ID_WIDTH": { + "value": "12" + }, + "PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": { + "value": "0" + }, + "PCW_M_AXI_GP0_THREAD_ID_WIDTH": { + "value": "12" + }, + "PCW_NAND_CYCLES_T_AR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_CLR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_REA": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_RR": { + "value": "1" + }, + "PCW_NAND_CYCLES_T_WC": { + "value": "11" + }, + "PCW_NAND_CYCLES_T_WP": { + "value": "1" + }, + "PCW_NAND_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_NOR_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_CS1_WE_TIME": { + "value": "0" + }, + "PCW_NOR_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_NOR_SRAM_CS0_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS0_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS0_WE_TIME": { + "value": "0" + }, + "PCW_NOR_SRAM_CS1_T_CEOE": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_PC": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_RC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_TR": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_T_WC": { + "value": "11" + }, + "PCW_NOR_SRAM_CS1_T_WP": { + "value": "1" + }, + "PCW_NOR_SRAM_CS1_WE_TIME": { + "value": "0" + }, + "PCW_OVERRIDE_BASIC_CLOCK": { + "value": "0" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY0": { + "value": "0.080" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY1": { + "value": "0.063" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY2": { + "value": "0.057" + }, + "PCW_PACKAGE_DDR_BOARD_DELAY3": { + "value": "0.068" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": { + "value": "-0.047" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": { + "value": "-0.025" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": { + "value": "-0.006" + }, + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": { + "value": "-0.017" + }, + "PCW_PACKAGE_NAME": { + "value": "clg400" + }, + "PCW_PCAP_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_PERIPHERAL_BOARD_PRESET": { + "value": "None" + }, + "PCW_PJTAG_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_PLL_BYPASSMODE_ENABLE": { + "value": "0" + }, + "PCW_PRESET_BANK0_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PRESET_BANK1_VOLTAGE": { + "value": "LVCMOS 3.3V" + }, + "PCW_PS7_SI_REV": { + "value": "PRODUCTION" + }, + "PCW_QSPI_INTERNAL_HIGHADDRESS": { + "value": "0xFCFFFFFF" + }, + "PCW_QSPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SD0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SD1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SDIO_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_SMC_CYCLE_T0": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T1": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T2": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T3": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T4": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T5": { + "value": "NA" + }, + "PCW_SMC_CYCLE_T6": { + "value": "NA" + }, + "PCW_SMC_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SMC_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_S_AXI_HP0_DATA_WIDTH": { + "value": "64" + }, + "PCW_S_AXI_HP0_ID_WIDTH": { + "value": "6" + }, + "PCW_TPIU_PERIPHERAL_CLKSRC": { + "value": "External" + }, + "PCW_TRACE_INTERNAL_WIDTH": { + "value": "2" + }, + "PCW_TRACE_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC0_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_TTC1_CLK0_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK1_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_CLK2_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_TTC1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_UART0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_UART1_BASEADDR": { + "value": "0xE0001000" + }, + "PCW_UART1_BAUD_RATE": { + "value": "115200" + }, + "PCW_UART1_GRP_FULL_ENABLE": { + "value": "0" + }, + "PCW_UART1_HIGHADDR": { + "value": "0xE0001FFF" + }, + "PCW_UART1_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_UART1_UART1_IO": { + "value": "MIO 48 .. 49" + }, + "PCW_UART_PERIPHERAL_CLKSRC": { + "value": "IO PLL" + }, + "PCW_UART_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_UART_PERIPHERAL_VALID": { + "value": "1" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "525.000000" + }, + "PCW_UIPARAM_DDR_ADV_ENABLE": { + "value": "0" + }, + "PCW_UIPARAM_DDR_AL": { + "value": "0" + }, + "PCW_UIPARAM_DDR_BL": { + "value": "8" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY0": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY1": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY2": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BOARD_DELAY3": { + "value": "0.25" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "32 Bit" + }, + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": { + "value": "54.563" + }, + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": { + "value": "54.563" + }, + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": { + "value": "54.563" + }, + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": { + "value": "54.563" + }, + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": { + "value": "101.239" + }, + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": { + "value": "79.5025" + }, + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": { + "value": "60.536" + }, + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": { + "value": "71.7715" + }, + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": { + "value": "0.0" + }, + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": { + "value": "104.5365" + }, + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": { + "value": "70.676" + }, + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": { + "value": "59.1615" + }, + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": { + "value": "0" + }, + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": { + "value": "81.319" + }, + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": { + "value": "160" + }, + "PCW_UIPARAM_DDR_ENABLE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_FREQ_MHZ": { + "value": "525" + }, + "PCW_UIPARAM_DDR_HIGH_TEMP": { + "value": "Normal (0-85)" + }, + "PCW_UIPARAM_DDR_MEMORY_TYPE": { + "value": "DDR 3" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41K128M16 JT-125" + }, + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": { + "value": "1" + }, + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": { + "value": "1" + }, + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": { + "value": "0" + }, + "PCW_UIPARAM_GENERATE_SUMMARY": { + "value": "NA" + }, + "PCW_USB0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_USB1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_USB_RESET_POLARITY": { + "value": "Active Low" + }, + "PCW_USE_AXI_FABRIC_IDLE": { + "value": "0" + }, + "PCW_USE_AXI_NONSECURE": { + "value": "0" + }, + "PCW_USE_CORESIGHT": { + "value": "0" + }, + "PCW_USE_CROSS_TRIGGER": { + "value": "0" + }, + "PCW_USE_CR_FABRIC": { + "value": "1" + }, + "PCW_USE_DDR_BYPASS": { + "value": "0" + }, + "PCW_USE_DEBUG": { + "value": "0" + }, + "PCW_USE_DMA0": { + "value": "0" + }, + "PCW_USE_DMA1": { + "value": "0" + }, + "PCW_USE_DMA2": { + "value": "0" + }, + "PCW_USE_DMA3": { + "value": "0" + }, + "PCW_USE_EXPANDED_IOP": { + "value": "0" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "0" + }, + "PCW_USE_HIGH_OCM": { + "value": "0" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + }, + "PCW_USE_M_AXI_GP1": { + "value": "0" + }, + "PCW_USE_PROC_EVENT_BUS": { + "value": "0" + }, + "PCW_USE_PS_SLCR_REGISTERS": { + "value": "0" + }, + "PCW_USE_S_AXI_ACP": { + "value": "0" + }, + "PCW_USE_S_AXI_GP0": { + "value": "0" + }, + "PCW_USE_S_AXI_GP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP0": { + "value": "1" + }, + "PCW_USE_S_AXI_HP1": { + "value": "0" + }, + "PCW_USE_S_AXI_HP2": { + "value": "0" + }, + "PCW_USE_S_AXI_HP3": { + "value": "0" + }, + "PCW_USE_TRACE": { + "value": "0" + }, + "PCW_VALUE_SILVERSION": { + "value": "3" + }, + "PCW_WDT_PERIPHERAL_CLKSRC": { + "value": "CPU_1X" + }, + "PCW_WDT_PERIPHERAL_DIVISOR0": { + "value": "1" + }, + "PCW_WDT_PERIPHERAL_ENABLE": { + "value": "0" + }, + "preset": { + "value": "None" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + }, + "S_AXI_HP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "memory_map_ref": "S_AXI_HP0" + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "axi_dma_0": { + "vlnv": "xilinx.com:ip:axi_dma:7.1", + "xci_name": "dmaSuperSystem_axi_dma_0_0", + "xci_path": "ip\\dmaSuperSystem_axi_dma_0_0\\dmaSuperSystem_axi_dma_0_0.xci", + "inst_hier_path": "axi_dma_0", + "parameters": { + "c_include_sg": { + "value": "0" + } + }, + "interface_ports": { + "M_AXI_MM2S": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_MM2S", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + }, + "M_AXI_S2MM": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data_S2MM", + "base_address": { + "minimum": "0x00000000", + "maximum": "0xFFFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data_MM2S": { + "range": "4G", + "width": "32" + }, + "Data_S2MM": { + "range": "4G", + "width": "32" + } + } + } + }, + "ps7_0_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\dmaSuperSystem_ps7_0_axi_periph_1\\dmaSuperSystem_ps7_0_axi_periph_1.xci", + "inst_hier_path": "ps7_0_axi_periph", + "xci_name": "dmaSuperSystem_ps7_0_axi_periph_1", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "dmaSuperSystem_auto_pc_0", + "xci_path": "ip\\dmaSuperSystem_auto_pc_0\\dmaSuperSystem_auto_pc_0.xci", + "inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "ps7_0_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M00_AXI", + "s00_couplers/M_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "ps7_0_axi_periph_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "ps7_0_axi_periph_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + }, + "rst_ps7_0_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "xci_name": "dmaSuperSystem_rst_ps7_0_100M_0", + "xci_path": "ip\\dmaSuperSystem_rst_ps7_0_100M_0\\dmaSuperSystem_rst_ps7_0_100M_0.xci", + "inst_hier_path": "rst_ps7_0_100M" + }, + "axi_mem_intercon": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip\\dmaSuperSystem_axi_mem_intercon_0\\dmaSuperSystem_axi_mem_intercon_0.xci", + "inst_hier_path": "axi_mem_intercon", + "xci_name": "dmaSuperSystem_axi_mem_intercon_0", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "2" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S01_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S01_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S01_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S01_ARESETN" + } + } + }, + "S01_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "xbar": { + "vlnv": "xilinx.com:ip:axi_crossbar:2.1", + "xci_name": "dmaSuperSystem_xbar_0", + "xci_path": "ip\\dmaSuperSystem_xbar_0\\dmaSuperSystem_xbar_0.xci", + "inst_hier_path": "axi_mem_intercon/xbar", + "parameters": { + "NUM_MI": { + "value": "1" + }, + "NUM_SI": { + "value": "2" + }, + "STRATEGY": { + "value": "0" + } + }, + "interface_ports": { + "S00_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + }, + "S01_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M00_AXI" + ] + } + } + }, + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "dmaSuperSystem_auto_us_0", + "xci_path": "ip\\dmaSuperSystem_auto_us_0\\dmaSuperSystem_auto_us_0.xci", + "inst_hier_path": "axi_mem_intercon/s00_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "64" + }, + "SI_DATA_WIDTH": { + "value": "32" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_us/M_AXI" + ] + }, + "s00_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "s01_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_us": { + "vlnv": "xilinx.com:ip:axi_dwidth_converter:2.1", + "xci_name": "dmaSuperSystem_auto_us_1", + "xci_path": "ip\\dmaSuperSystem_auto_us_1\\dmaSuperSystem_auto_us_1.xci", + "inst_hier_path": "axi_mem_intercon/s01_couplers/auto_us", + "parameters": { + "MI_DATA_WIDTH": { + "value": "64" + }, + "SI_DATA_WIDTH": { + "value": "32" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_us_to_s01_couplers": { + "interface_ports": [ + "M_AXI", + "auto_us/M_AXI" + ] + }, + "s01_couplers_to_auto_us": { + "interface_ports": [ + "S_AXI", + "auto_us/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_us/s_axi_aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_us/s_axi_aresetn" + ] + } + } + }, + "m00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "xci_name": "dmaSuperSystem_auto_pc_1", + "xci_path": "ip\\dmaSuperSystem_auto_pc_1\\dmaSuperSystem_auto_pc_1.xci", + "inst_hier_path": "axi_mem_intercon/m00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI3" + }, + "SI_PROTOCOL": { + "value": "AXI4" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_m00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "m00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "axi_mem_intercon_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "axi_mem_intercon_to_s01_couplers": { + "interface_ports": [ + "S01_AXI", + "s01_couplers/S_AXI" + ] + }, + "m00_couplers_to_axi_mem_intercon": { + "interface_ports": [ + "M00_AXI", + "m00_couplers/M_AXI" + ] + }, + "s00_couplers_to_xbar": { + "interface_ports": [ + "s00_couplers/M_AXI", + "xbar/S00_AXI" + ] + }, + "s01_couplers_to_xbar": { + "interface_ports": [ + "s01_couplers/M_AXI", + "xbar/S01_AXI" + ] + }, + "xbar_to_m00_couplers": { + "interface_ports": [ + "xbar/M00_AXI", + "m00_couplers/S_AXI" + ] + } + }, + "nets": { + "axi_mem_intercon_ACLK_net": { + "ports": [ + "ACLK", + "xbar/aclk", + "s00_couplers/S_ACLK", + "s01_couplers/S_ACLK", + "s00_couplers/M_ACLK", + "s01_couplers/M_ACLK", + "m00_couplers/M_ACLK", + "m00_couplers/S_ACLK" + ] + }, + "axi_mem_intercon_ARESETN_net": { + "ports": [ + "ARESETN", + "xbar/aresetn", + "s00_couplers/S_ARESETN", + "s01_couplers/S_ARESETN", + "s00_couplers/M_ARESETN", + "s01_couplers/M_ARESETN", + "m00_couplers/M_ARESETN", + "m00_couplers/S_ARESETN" + ] + } + } + }, + "system_ila_0": { + "vlnv": "xilinx.com:ip:system_ila:1.1", + "xci_name": "dmaSuperSystem_system_ila_0_0", + "xci_path": "ip\\dmaSuperSystem_system_ila_0_0\\dmaSuperSystem_system_ila_0_0.xci", + "inst_hier_path": "system_ila_0", + "parameters": { + "C_MON_TYPE": { + "value": "INTERFACE" + }, + "C_NUM_MONITOR_SLOTS": { + "value": "2" + }, + "C_SLOT_0_APC_EN": { + "value": "0" + }, + "C_SLOT_0_AXI_DATA_SEL": { + "value": "1" + }, + "C_SLOT_0_AXI_TRIG_SEL": { + "value": "1" + }, + "C_SLOT_0_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + }, + "C_SLOT_1_APC_EN": { + "value": "0" + }, + "C_SLOT_1_AXI_DATA_SEL": { + "value": "1" + }, + "C_SLOT_1_AXI_TRIG_SEL": { + "value": "1" + }, + "C_SLOT_1_INTF_TYPE": { + "value": "xilinx.com:interface:axis_rtl:1.0" + } + }, + "interface_ports": { + "SLOT_0_AXIS": { + "mode": "Monitor", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + }, + "SLOT_1_AXIS": { + "mode": "Monitor", + "vlnv_bus_definition": "xilinx.com:interface:axis:1.0", + "vlnv": "xilinx.com:interface:axis_rtl:1.0" + } + } + }, + "DummyKvPairFifo_0": { + "vlnv": "bme.hu:user:DummyKvPairFifo:1.1", + "xci_name": "dmaSuperSystem_DummyKvPairFifo_0_2", + "xci_path": "ip\\dmaSuperSystem_DummyKvPairFifo_0_2\\dmaSuperSystem_DummyKvPairFifo_0_2.xci", + "inst_hier_path": "DummyKvPairFifo_0" + } + }, + "interface_nets": { + "axi_dma_0_M_AXIS_MM2S": { + "interface_ports": [ + "axi_dma_0/M_AXIS_MM2S", + "DummyKvPairFifo_0/axis_s", + "system_ila_0/SLOT_0_AXIS" + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + }, + "MARK_DEBUG": { + "value": "true" + } + } + }, + "axi_dma_0_M_AXI_MM2S": { + "interface_ports": [ + "axi_dma_0/M_AXI_MM2S", + "axi_mem_intercon/S00_AXI" + ] + }, + "axi_dma_0_M_AXI_S2MM": { + "interface_ports": [ + "axi_dma_0/M_AXI_S2MM", + "axi_mem_intercon/S01_AXI" + ] + }, + "axi_mem_intercon_M00_AXI": { + "interface_ports": [ + "axi_mem_intercon/M00_AXI", + "processing_system7_0/S_AXI_HP0" + ] + }, + "inverter_0_m_axis": { + "interface_ports": [ + "DummyKvPairFifo_0/axi_m", + "axi_dma_0/S_AXIS_S2MM", + "system_ila_0/SLOT_1_AXIS" + ], + "hdl_attributes": { + "DEBUG": { + "value": "true" + }, + "MARK_DEBUG": { + "value": "true" + } + } + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7_0/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7_0/FIXED_IO" + ] + }, + "processing_system7_0_M_AXI_GP0": { + "interface_ports": [ + "processing_system7_0/M_AXI_GP0", + "ps7_0_axi_periph/S00_AXI" + ] + }, + "ps7_0_axi_periph_M00_AXI": { + "interface_ports": [ + "ps7_0_axi_periph/M00_AXI", + "axi_dma_0/S_AXI_LITE" + ] + } + }, + "nets": { + "processing_system7_0_FCLK_CLK0": { + "ports": [ + "processing_system7_0/FCLK_CLK0", + "processing_system7_0/M_AXI_GP0_ACLK", + "ps7_0_axi_periph/S00_ACLK", + "rst_ps7_0_100M/slowest_sync_clk", + "axi_dma_0/s_axi_lite_aclk", + "ps7_0_axi_periph/M00_ACLK", + "ps7_0_axi_periph/ACLK", + "axi_dma_0/m_axi_s2mm_aclk", + "axi_dma_0/m_axi_mm2s_aclk", + "axi_mem_intercon/S00_ACLK", + "processing_system7_0/S_AXI_HP0_ACLK", + "axi_mem_intercon/M00_ACLK", + "axi_mem_intercon/ACLK", + "axi_mem_intercon/S01_ACLK", + "system_ila_0/clk", + "DummyKvPairFifo_0/clock" + ] + }, + "processing_system7_0_FCLK_RESET0_N": { + "ports": [ + "processing_system7_0/FCLK_RESET0_N", + "rst_ps7_0_100M/ext_reset_in" + ] + }, + "rst_ps7_0_100M_peripheral_aresetn": { + "ports": [ + "rst_ps7_0_100M/peripheral_aresetn", + "ps7_0_axi_periph/S00_ARESETN", + "axi_dma_0/axi_resetn", + "ps7_0_axi_periph/M00_ARESETN", + "ps7_0_axi_periph/ARESETN", + "axi_mem_intercon/S00_ARESETN", + "axi_mem_intercon/M00_ARESETN", + "axi_mem_intercon/ARESETN", + "axi_mem_intercon/S01_ARESETN", + "system_ila_0/resetn", + "DummyKvPairFifo_0/reset" + ] + } + }, + "addressing": { + "/processing_system7_0": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_dma_0_Reg": { + "address_block": "/axi_dma_0/S_AXI_LITE/Reg", + "offset": "0x40400000", + "range": "64K" + } + } + } + } + }, + "/axi_dma_0": { + "address_spaces": { + "Data_MM2S": { + "segments": { + "SEG_processing_system7_0_HP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "512M" + } + } + }, + "Data_S2MM": { + "segments": { + "SEG_processing_system7_0_HP0_DDR_LOWOCM": { + "address_block": "/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM", + "offset": "0x00000000", + "range": "512M" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bda b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bda new file mode 100644 index 0000000..b953c92 --- /dev/null +++ b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/dmaSuperSystem.bda @@ -0,0 +1,103 @@ + + + + + + + + + + + + + + + + + + + + + + + + 0x40400000 + C_BASEADDR + 0x4040FFFF + C_HIGHADDR + Data + /processing_system7_0 + M_AXI_GP0 + SEG_axi_dma_0_Reg + xilinx.com:ip:processing_system7:5.5 + both + /axi_dma_0 + S_AXI_LITE + Reg + xilinx.com:ip:axi_dma:7.1 + register + AC + + + 0x00000000 + C_BASEADDR + 0x1FFFFFFF + C_HIGHADDR + Data_S2MM + /axi_dma_0 + M_AXI_S2MM + SEG_processing_system7_0_HP0_DDR_LOWOCM + xilinx.com:ip:axi_dma:7.1 + both + /processing_system7_0 + S_AXI_HP0 + HP0_DDR_LOWOCM + xilinx.com:ip:processing_system7:5.5 + memory + AC + + + dmaSuperSystem + BC + + + 0x00000000 + C_BASEADDR + 0x1FFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_processing_system7_0_HP0_DDR_LOWOCM + xilinx.com:ip:axi_dma:7.1 + both + /processing_system7_0 + S_AXI_HP0 + HP0_DDR_LOWOCM + xilinx.com:ip:processing_system7:5.5 + memory + AC + + + 2 + dmaSuperSystem + VR + + + active + 2 + PM + + + + + 2 + + + 2 + + + 2 + + + diff --git a/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_DummyKvPairFifo_0_2/dmaSuperSystem_DummyKvPairFifo_0_2.xci b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_DummyKvPairFifo_0_2/dmaSuperSystem_DummyKvPairFifo_0_2.xci new file mode 100644 index 0000000..444bb2c --- /dev/null +++ b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_DummyKvPairFifo_0_2/dmaSuperSystem_DummyKvPairFifo_0_2.xci @@ -0,0 +1,208 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dmaSuperSystem_DummyKvPairFifo_0_2 + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ui/bd_ac33bd72.ui b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ui/bd_ac33bd72.ui new file mode 100644 index 0000000..468546f --- /dev/null +++ b/Vivado/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ui/bd_ac33bd72.ui @@ -0,0 +1,37 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.839389", + "Default View_TopLeft":"245,-187", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS-threadsafe +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 7 -x 2370 -y 400 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 7 -x 2370 -y 420 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 5 -x 1870 -y 440 -defaultsOSRD +preplace inst axi_dma_0 -pg 1 -lvl 3 -x 1120 -y 140 -defaultsOSRD +preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 750 -y 470 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 180 -y 460 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 4 -x 1480 -y 170 -defaultsOSRD +preplace inst system_ila_0 -pg 1 -lvl 6 -x 2240 -y 120 -defaultsOSRD +preplace inst DummyKvPairFifo_0 -pg 1 -lvl 2 -x 750 -y 50 -defaultsOSRD +preplace netloc processing_system7_0_FCLK_CLK0 1 0 6 0 560 350 130 910 10 1310 330 1640 330 2120 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 6 -10 340 NJ 340 NJ 340 NJ 340 NJ 340 2100 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 5 360 140 900 0 1330 0 N 0 2110 +preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 5 350 -30 N -30 1320 10 N 10 2120 +preplace netloc axi_dma_0_M_AXI_MM2S 1 3 1 N 80 +preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 N 100 +preplace netloc axi_mem_intercon_M00_AXI 1 4 1 1630 170n +preplace netloc inverter_0_m_axis 1 2 4 930 20 N 20 N 20 2100 +preplace netloc processing_system7_0_DDR 1 5 2 NJ 400 N +preplace netloc processing_system7_0_FIXED_IO 1 5 2 NJ 420 N +preplace netloc processing_system7_0_M_AXI_GP0 1 1 5 370 320 NJ 320 NJ 320 NJ 320 2110 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 920 90n +levelinfo -pg 1 -30 180 750 1120 1480 1870 2240 2370 +pagesize -pg 1 -db -bbox -sgen -30 -150 2490 590 +" +} +{ + "da_axi4_cnt":"4", + "da_clkrst_cnt":"6", + "da_ps7_cnt":"1" +} diff --git a/Vivado/LSM-Compactron3000/LSM-Compactron3000.xpr b/Vivado/LSM-Compactron3000/LSM-Compactron3000.xpr new file mode 100644 index 0000000..92d9e2c --- /dev/null +++ b/Vivado/LSM-Compactron3000/LSM-Compactron3000.xpr @@ -0,0 +1,308 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/imports/hdl/DummyKvPairFifo.v b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/imports/hdl/DummyKvPairFifo.v new file mode 100644 index 0000000..bf605ab --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/imports/hdl/DummyKvPairFifo.v @@ -0,0 +1,755 @@ +module DummyEncoder( + input clock, + input reset, + output io_input_deq_ready, + input io_input_deq_valid, + input [31:0] io_input_deq_bits, + input io_input_lastOutput, + input io_input_metadataValid, + output [31:0] io_output_axi_m_tdata, + output io_output_axi_m_tvalid, + input io_output_axi_m_tready +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + reg [1:0] state; // @[DummyEncoder.scala 24:24] + reg [31:0] status; // @[DummyEncoder.scala 25:25] + wire [31:0] _status_T_3 = {status[31:16],io_input_deq_bits[7:0],status[7:0]}; // @[Cat.scala 33:92] + wire [31:0] _status_T_7 = {status[31:24],io_input_deq_bits[7:0],status[15:0]}; // @[Cat.scala 33:92] + wire [1:0] _GEN_3 = io_output_axi_m_tready ? 2'h3 : state; // @[DummyEncoder.scala 43:43 44:23 24:24] + wire [1:0] _GEN_4 = io_input_lastOutput & io_output_axi_m_tready ? 2'h0 : state; // @[DummyEncoder.scala 49:66 50:23 24:24] + wire [1:0] _GEN_5 = 2'h3 == state ? _GEN_4 : state; // @[DummyEncoder.scala 27:20 24:24] + wire _io_output_axi_m_tdata_T = state == 2'h2; // @[DummyEncoder.scala 56:40] + assign io_input_deq_ready = state == 2'h3 & io_output_axi_m_tready; // @[DummyEncoder.scala 55:48] + assign io_output_axi_m_tdata = state == 2'h2 ? status : io_input_deq_bits; // @[DummyEncoder.scala 56:33] + assign io_output_axi_m_tvalid = _io_output_axi_m_tdata_T | io_input_deq_valid; // @[DummyEncoder.scala 57:54] + always @(posedge clock) begin + if (reset) begin // @[DummyEncoder.scala 24:24] + state <= 2'h0; // @[DummyEncoder.scala 24:24] + end else if (2'h0 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 29:43] + state <= 2'h1; // @[DummyEncoder.scala 31:23] + end + end else if (2'h1 == state) begin // @[DummyEncoder.scala 27:20] + state <= 2'h2; // @[DummyEncoder.scala 39:19] + end else if (2'h2 == state) begin // @[DummyEncoder.scala 27:20] + state <= _GEN_3; + end else begin + state <= _GEN_5; + end + if (reset) begin // @[DummyEncoder.scala 25:25] + status <= 32'h0; // @[DummyEncoder.scala 25:25] + end else if (2'h0 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 29:43] + status <= _status_T_3; // @[DummyEncoder.scala 30:24] + end + end else if (2'h1 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 36:43] + status <= _status_T_7; // @[DummyEncoder.scala 37:24] + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + status = _RAND_1[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummyDecoder( + input clock, + input reset, + input [31:0] io_input_axi_s_tdata, + input io_input_axi_s_tvalid, + output io_input_axi_s_tready, + output io_output_enq_valid, + output [31:0] io_output_enq_bits, + output io_output_lastInput, + output io_output_isInputKey +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + reg [1:0] state; // @[DummyDecoder.scala 27:24] + reg [31:0] status; // @[DummyDecoder.scala 28:25] + reg [7:0] counter; // @[DummyDecoder.scala 32:26] + wire [7:0] keyLen = status[15:8] - 8'h1; // @[DummyDecoder.scala 35:32] + wire [7:0] valueLen = status[23:16] - 8'h1; // @[DummyDecoder.scala 36:35] + wire _T_2 = io_input_axi_s_tvalid & io_input_axi_s_tready; // @[DummyDecoder.scala 48:41] + wire [7:0] _counter_T_1 = counter + 8'h1; // @[DummyDecoder.scala 49:36] + wire [1:0] _GEN_2 = counter == keyLen ? 2'h2 : state; // @[DummyDecoder.scala 27:24 51:43 52:27] + wire [7:0] _GEN_3 = counter == keyLen ? 8'h0 : _counter_T_1; // @[DummyDecoder.scala 49:25 51:43 53:29] + wire _T_6 = counter == valueLen; // @[DummyDecoder.scala 62:31] + wire [1:0] _GEN_6 = counter == valueLen ? 2'h0 : state; // @[DummyDecoder.scala 27:24 62:45 63:27] + wire [7:0] _GEN_7 = counter == valueLen ? 8'h0 : _counter_T_1; // @[DummyDecoder.scala 60:25 62:45 64:29] + wire [7:0] _GEN_9 = _T_2 ? _GEN_7 : counter; // @[DummyDecoder.scala 32:26 59:67] + wire [1:0] _GEN_10 = _T_2 ? _GEN_6 : state; // @[DummyDecoder.scala 27:24 59:67] + wire _io_output_enq_valid_T_1 = state == 2'h2; // @[DummyDecoder.scala 75:56] + assign io_input_axi_s_tready = 1'h1; // @[DummyDecoder.scala 72:27] + assign io_output_enq_valid = (state == 2'h1 | state == 2'h2) & io_input_axi_s_tvalid; // @[DummyDecoder.scala 75:71] + assign io_output_enq_bits = io_input_axi_s_tdata; // @[DummyDecoder.scala 76:24] + assign io_output_lastInput = _io_output_enq_valid_T_1 & _T_6; // @[DummyDecoder.scala 78:48] + assign io_output_isInputKey = state == 2'h1; // @[DummyDecoder.scala 77:35] + always @(posedge clock) begin + if (reset) begin // @[DummyDecoder.scala 27:24] + state <= 2'h0; // @[DummyDecoder.scala 27:24] + end else if (2'h0 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid) begin // @[DummyDecoder.scala 41:42] + state <= 2'h1; // @[DummyDecoder.scala 42:23] + end + end else if (2'h1 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid & io_input_axi_s_tready) begin // @[DummyDecoder.scala 48:67] + state <= _GEN_2; + end + end else if (2'h2 == state) begin // @[DummyDecoder.scala 39:20] + state <= _GEN_10; + end + if (reset) begin // @[DummyDecoder.scala 28:25] + status <= 32'h0; // @[DummyDecoder.scala 28:25] + end else if (2'h0 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid) begin // @[DummyDecoder.scala 41:42] + status <= io_input_axi_s_tdata; // @[DummyDecoder.scala 43:24] + end + end + if (reset) begin // @[DummyDecoder.scala 32:26] + counter <= 8'h0; // @[DummyDecoder.scala 32:26] + end else if (!(2'h0 == state)) begin // @[DummyDecoder.scala 39:20] + if (2'h1 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid & io_input_axi_s_tready) begin // @[DummyDecoder.scala 48:67] + counter <= _GEN_3; + end + end else if (2'h2 == state) begin // @[DummyDecoder.scala 39:20] + counter <= _GEN_9; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + status = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + counter = _RAND_2[7:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module KVRingBuffer( + input clock, + input reset, + input io_enq_valid, + input [31:0] io_enq_bits, + input io_lastInput, + input io_isInputKey, + input io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits, + output io_lastOutput, + output io_metadataValid +); +`ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] _RAND_2; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_MEM_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_1; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; +`endif // RANDOMIZE_REG_INIT + reg [31:0] mem [0:1279]; // @[KvRingBuffer.scala 84:26] + wire mem_data_en; // @[KvRingBuffer.scala 180:{24,24} 84:{26,26}] + reg [10:0] mem_data_addr; // @[KvRingBuffer.scala 84:26] + wire [31:0] mem_data_data; // @[KvRingBuffer.scala 84:26] + wire [31:0] mem_MPORT_data; // @[KvRingBuffer.scala 84:26 129:72] + wire [10:0] mem_MPORT_addr; // @[KvRingBuffer.scala 84:26] + wire mem_MPORT_mask; // @[KvRingBuffer.scala 84:26] + wire mem_MPORT_en; // @[KvRingBuffer.scala 84:26] + reg [1:0] readPtr; // @[KvRingBuffer.scala 75:29] + wire [1:0] _nextVal_T_2 = readPtr + 2'h1; // @[KvRingBuffer.scala 76:63] + wire [1:0] nextRead = readPtr == 2'h3 ? 2'h0 : _nextVal_T_2; // @[KvRingBuffer.scala 76:26] + reg [3:0] outputStateReg; // @[KvRingBuffer.scala 122:33] + wire _GEN_126 = 4'ha == outputStateReg ? io_deq_ready : 4'hb == outputStateReg & io_deq_ready; // @[KvRingBuffer.scala 183:28] + wire _GEN_131 = 4'h9 == outputStateReg ? 1'h0 : _GEN_126; // @[KvRingBuffer.scala 183:28] + wire _GEN_137 = 4'h8 == outputStateReg ? 1'h0 : _GEN_131; // @[KvRingBuffer.scala 183:28] + wire _GEN_142 = 4'h7 == outputStateReg ? 1'h0 : _GEN_137; // @[KvRingBuffer.scala 183:28] + wire _GEN_147 = 4'h6 == outputStateReg ? 1'h0 : _GEN_142; // @[KvRingBuffer.scala 183:28] + wire _GEN_153 = 4'h5 == outputStateReg ? 1'h0 : _GEN_147; // @[KvRingBuffer.scala 183:28] + wire _GEN_159 = 4'h4 == outputStateReg ? 1'h0 : _GEN_153; // @[KvRingBuffer.scala 183:28] + wire _GEN_166 = 4'h3 == outputStateReg ? 1'h0 : _GEN_159; // @[KvRingBuffer.scala 183:28] + wire _GEN_174 = 4'h2 == outputStateReg ? 1'h0 : _GEN_166; // @[KvRingBuffer.scala 183:28] + wire _GEN_182 = 4'h1 == outputStateReg ? 1'h0 : _GEN_174; // @[KvRingBuffer.scala 183:28] + wire incrRead = 4'h0 == outputStateReg ? 1'h0 : _GEN_182; // @[KvRingBuffer.scala 183:28] + reg [1:0] writePtr; // @[KvRingBuffer.scala 75:29] + wire [1:0] _nextVal_T_5 = writePtr + 2'h1; // @[KvRingBuffer.scala 76:63] + wire [1:0] nextWrite = writePtr == 2'h3 ? 2'h0 : _nextVal_T_5; // @[KvRingBuffer.scala 76:26] + reg [1:0] inputStateReg; // @[KvRingBuffer.scala 121:32] + wire _GEN_25 = 2'h1 == inputStateReg ? 1'h0 : 2'h2 == inputStateReg; // @[KvRingBuffer.scala 135:27] + wire incrWrite = 2'h0 == inputStateReg ? 1'h0 : _GEN_25; // @[KvRingBuffer.scala 135:27] + reg [9:0] writeKeyChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_8 = writeKeyChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] writeValueChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_11 = writeValueChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] readKeyChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_14 = readKeyChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] readValueChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_17 = readValueChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [31:0] keyLen; // @[KvRingBuffer.scala 108:25] + reg [31:0] valueLen; // @[KvRingBuffer.scala 109:27] + reg emptyReg; // @[KvRingBuffer.scala 111:27] + reg fullReg; // @[KvRingBuffer.scala 112:26] + reg [31:0] writeReg; // @[KvRingBuffer.scala 124:27] + wire _writeDataPtr_T = inputStateReg == 2'h0; // @[KvRingBuffer.scala 126:42] + wire [2:0] _writeDataPtr_T_1 = io_isInputKey ? 3'h2 : 3'h6; // @[KvRingBuffer.scala 126:60] + wire [9:0] _writeDataPtr_T_2 = io_isInputKey ? writeKeyChunkPtr : writeValueChunkPtr; // @[KvRingBuffer.scala 126:152] + wire [9:0] _GEN_191 = {{7'd0}, _writeDataPtr_T_1}; // @[KvRingBuffer.scala 126:147] + wire [9:0] _writeDataPtr_T_4 = _GEN_191 + _writeDataPtr_T_2; // @[KvRingBuffer.scala 126:147] + wire [9:0] writeDataPtr = inputStateReg == 2'h0 ? _writeDataPtr_T_4 : 10'h0; // @[KvRingBuffer.scala 126:27] + wire metadataOffsetPtr = inputStateReg == 2'h2; // @[KvRingBuffer.scala 127:47] + wire [5:0] _T = writePtr * 4'h8; // @[KvRingBuffer.scala 129:24] + wire [9:0] _GEN_192 = {{4'd0}, _T}; // @[KvRingBuffer.scala 129:33] + wire [9:0] _T_2 = _GEN_192 + writeDataPtr; // @[KvRingBuffer.scala 129:33] + wire [9:0] _GEN_193 = {{9'd0}, metadataOffsetPtr}; // @[KvRingBuffer.scala 129:48] + wire [9:0] _T_4 = _T_2 + _GEN_193; // @[KvRingBuffer.scala 129:48] + wire [1:0] _GEN_6 = io_lastInput ? 2'h1 : inputStateReg; // @[KvRingBuffer.scala 121:32 144:40 145:39] + wire [31:0] _GEN_7 = io_lastInput ? {{22'd0}, writeKeyChunkPtr} : writeReg; // @[KvRingBuffer.scala 124:27 144:40 146:34] + wire _GEN_16 = 2'h2 == inputStateReg ? 1'h0 : emptyReg; // @[KvRingBuffer.scala 135:27 160:22 111:27] + wire _GEN_24 = 2'h1 == inputStateReg ? emptyReg : _GEN_16; // @[KvRingBuffer.scala 111:27 135:27] + wire _GEN_33 = 2'h0 == inputStateReg ? emptyReg : _GEN_24; // @[KvRingBuffer.scala 111:27 135:27] + wire [5:0] _readFullPtr_T = readPtr * 4'h8; // @[KvRingBuffer.scala 179:31] + wire [9:0] _GEN_194 = {{4'd0}, _readFullPtr_T}; // @[KvRingBuffer.scala 179:40] + wire [9:0] _readFullPtr_T_2 = _GEN_194 + readValueChunkPtr; // @[KvRingBuffer.scala 179:40] + wire [9:0] readFullPtr = _readFullPtr_T_2 + readKeyChunkPtr; // @[KvRingBuffer.scala 179:60] + reg [31:0] shadowReg; // @[KvRingBuffer.scala 181:28] + wire [31:0] _GEN_48 = mem_data_data; // @[KvRingBuffer.scala 200:42 201:24 108:25] + wire [9:0] _GEN_52 = keyLen == 32'h1 ? 10'h0 : readValueChunkPtr; // @[KvRingBuffer.scala 213:38 215:39] + wire [2:0] _GEN_53 = keyLen == 32'h1 ? 3'h6 : 3'h1; // @[KvRingBuffer.scala 213:38 216:37 221:37] + wire [3:0] _GEN_54 = keyLen == 32'h1 ? 4'h6 : 4'h4; // @[KvRingBuffer.scala 213:38 218:36 222:36] + wire [9:0] _GEN_56 = {{7'd0}, _GEN_53}; // @[KvRingBuffer.scala 212:42] + wire [31:0] _T_26 = keyLen - 32'h1; // @[KvRingBuffer.scala 230:54] + wire [31:0] _GEN_195 = {{22'd0}, readKeyChunkPtr}; // @[KvRingBuffer.scala 230:43] + wire _T_27 = _GEN_195 == _T_26; // @[KvRingBuffer.scala 230:43] + wire _emptyReg_T = nextRead == writePtr; // @[KvRingBuffer.scala 232:46] + wire [3:0] _GEN_58 = _GEN_195 == _T_26 ? 4'h6 : outputStateReg; // @[KvRingBuffer.scala 230:61 231:40] + wire _GEN_59 = _GEN_195 == _T_26 ? nextRead == writePtr : _GEN_33; // @[KvRingBuffer.scala 230:61 232:34] + wire [9:0] _GEN_60 = _GEN_195 == _T_26 ? 10'h0 : readValueChunkPtr; // @[KvRingBuffer.scala 230:61 233:43] + wire [9:0] _GEN_61 = _GEN_195 == _T_26 ? 10'h6 : _nextVal_T_14; // @[KvRingBuffer.scala 230:61 234:41 236:41] + wire [3:0] _GEN_62 = io_deq_ready ? _GEN_58 : 4'h5; // @[KvRingBuffer.scala 229:36 241:36] + wire _GEN_63 = io_deq_ready ? _GEN_59 : _GEN_33; // @[KvRingBuffer.scala 229:36] + wire [9:0] _GEN_64 = io_deq_ready ? _GEN_60 : readValueChunkPtr; // @[KvRingBuffer.scala 229:36] + wire [9:0] _GEN_65 = io_deq_ready ? _GEN_61 : readKeyChunkPtr; // @[KvRingBuffer.scala 229:36] + wire [31:0] _GEN_66 = io_deq_ready ? shadowReg : mem_data_data; // @[KvRingBuffer.scala 181:28 229:36 240:31] + wire [3:0] _GEN_72 = _T_27 ? 4'h6 : 4'h4; // @[KvRingBuffer.scala 248:57 249:36 254:36] + wire [3:0] _GEN_76 = io_deq_ready ? _GEN_72 : outputStateReg; // @[KvRingBuffer.scala 247:57] + wire [3:0] _GEN_80 = valueLen == 32'h1 ? 4'ha : 4'h8; // @[KvRingBuffer.scala 266:48 267:44 269:44] + wire [9:0] _GEN_81 = valueLen == 32'h1 ? readValueChunkPtr : 10'h1; // @[KvRingBuffer.scala 266:48 270:47] + wire [3:0] _GEN_84 = io_deq_ready ? _GEN_80 : 4'h7; // @[KvRingBuffer.scala 262:36 275:36] + wire [9:0] _GEN_85 = io_deq_ready ? _GEN_81 : readValueChunkPtr; // @[KvRingBuffer.scala 262:36] + wire [3:0] _GEN_93 = io_deq_ready ? _GEN_80 : outputStateReg; // @[KvRingBuffer.scala 281:57] + wire [31:0] _T_44 = valueLen - 32'h1; // @[KvRingBuffer.scala 298:57] + wire [31:0] _GEN_197 = {{22'd0}, readValueChunkPtr}; // @[KvRingBuffer.scala 298:44] + wire _T_45 = _GEN_197 == _T_44; // @[KvRingBuffer.scala 298:44] + wire [3:0] _GEN_95 = _GEN_197 == _T_44 ? 4'ha : outputStateReg; // @[KvRingBuffer.scala 298:64 299:40] + wire _GEN_96 = _GEN_197 == _T_44 ? _emptyReg_T : _GEN_33; // @[KvRingBuffer.scala 298:64 303:34] + wire [9:0] _GEN_97 = _GEN_197 == _T_44 ? readValueChunkPtr : _nextVal_T_17; // @[KvRingBuffer.scala 298:64 305:43] + wire [3:0] _GEN_98 = io_deq_ready ? _GEN_95 : 4'h9; // @[KvRingBuffer.scala 297:36 310:36] + wire _GEN_99 = io_deq_ready ? _GEN_96 : _GEN_33; // @[KvRingBuffer.scala 297:36] + wire [9:0] _GEN_100 = io_deq_ready ? _GEN_97 : readValueChunkPtr; // @[KvRingBuffer.scala 297:36] + wire [3:0] _GEN_105 = _T_45 ? 4'ha : 4'h8; // @[KvRingBuffer.scala 317:60 318:36 324:36] + wire [3:0] _GEN_108 = io_deq_ready ? _GEN_105 : outputStateReg; // @[KvRingBuffer.scala 316:57] + wire [3:0] _GEN_111 = io_deq_ready ? 4'h0 : 4'hb; // @[KvRingBuffer.scala 332:36 333:36 341:36] + wire _GEN_112 = io_deq_ready ? _emptyReg_T : _GEN_33; // @[KvRingBuffer.scala 332:36 334:30] + wire [3:0] _GEN_118 = io_deq_ready ? 4'h0 : outputStateReg; // @[KvRingBuffer.scala 347:57 348:32] + wire [3:0] _GEN_121 = 4'hb == outputStateReg ? _GEN_118 : outputStateReg; // @[KvRingBuffer.scala 183:28] + wire _GEN_122 = 4'hb == outputStateReg ? _GEN_112 : _GEN_33; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_124 = 4'ha == outputStateReg ? _GEN_111 : _GEN_121; // @[KvRingBuffer.scala 183:28] + wire _GEN_125 = 4'ha == outputStateReg ? _GEN_112 : _GEN_122; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_127 = 4'ha == outputStateReg ? _GEN_66 : shadowReg; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_128 = 4'h9 == outputStateReg ? _GEN_108 : _GEN_124; // @[KvRingBuffer.scala 183:28] + wire _GEN_129 = 4'h9 == outputStateReg ? _GEN_99 : _GEN_125; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_130 = 4'h9 == outputStateReg ? _GEN_100 : readValueChunkPtr; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_132 = 4'h9 == outputStateReg ? shadowReg : _GEN_127; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_133 = 4'h8 == outputStateReg ? _GEN_98 : _GEN_128; // @[KvRingBuffer.scala 183:28] + wire _GEN_134 = 4'h8 == outputStateReg ? _GEN_99 : _GEN_129; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_135 = 4'h8 == outputStateReg ? _GEN_100 : _GEN_130; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_136 = 4'h8 == outputStateReg ? _GEN_66 : _GEN_132; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_138 = 4'h7 == outputStateReg ? _GEN_93 : _GEN_133; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_139 = 4'h7 == outputStateReg ? _GEN_85 : _GEN_135; // @[KvRingBuffer.scala 183:28] + wire _GEN_140 = 4'h7 == outputStateReg ? _GEN_33 : _GEN_134; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_141 = 4'h7 == outputStateReg ? shadowReg : _GEN_136; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_143 = 4'h6 == outputStateReg ? _GEN_84 : _GEN_138; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_144 = 4'h6 == outputStateReg ? _GEN_85 : _GEN_139; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_145 = 4'h6 == outputStateReg ? _GEN_66 : _GEN_141; // @[KvRingBuffer.scala 183:28] + wire _GEN_146 = 4'h6 == outputStateReg ? _GEN_33 : _GEN_140; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_148 = 4'h5 == outputStateReg ? _GEN_76 : _GEN_143; // @[KvRingBuffer.scala 183:28] + wire _GEN_149 = 4'h5 == outputStateReg ? _GEN_63 : _GEN_146; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_150 = 4'h5 == outputStateReg ? _GEN_64 : _GEN_144; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_151 = 4'h5 == outputStateReg ? _GEN_65 : readKeyChunkPtr; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_152 = 4'h5 == outputStateReg ? shadowReg : _GEN_145; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_154 = 4'h4 == outputStateReg ? _GEN_62 : _GEN_148; // @[KvRingBuffer.scala 183:28] + wire _GEN_155 = 4'h4 == outputStateReg ? _GEN_63 : _GEN_149; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_156 = 4'h4 == outputStateReg ? _GEN_64 : _GEN_150; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_157 = 4'h4 == outputStateReg ? _GEN_65 : _GEN_151; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_158 = 4'h4 == outputStateReg ? _GEN_66 : _GEN_152; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_160 = 4'h3 == outputStateReg ? mem_data_data : valueLen; // @[KvRingBuffer.scala 183:28 211:22 109:27] + wire [9:0] _GEN_161 = 4'h3 == outputStateReg ? _GEN_52 : _GEN_156; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_162 = 4'h3 == outputStateReg ? _GEN_56 : _GEN_157; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_163 = 4'h3 == outputStateReg ? _GEN_54 : _GEN_154; // @[KvRingBuffer.scala 183:28] + wire _GEN_164 = 4'h3 == outputStateReg ? _GEN_33 : _GEN_155; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_165 = 4'h3 == outputStateReg ? shadowReg : _GEN_158; // @[KvRingBuffer.scala 181:28 183:28] + wire _GEN_172 = 4'h2 == outputStateReg ? _GEN_33 : _GEN_164; // @[KvRingBuffer.scala 183:28] + wire _GEN_180 = 4'h1 == outputStateReg ? _GEN_33 : _GEN_172; // @[KvRingBuffer.scala 183:28] + wire _GEN_188 = 4'h0 == outputStateReg ? _GEN_33 : _GEN_180; // @[KvRingBuffer.scala 183:28] + wire _io_deq_valid_T_3 = outputStateReg == 4'h5; // @[KvRingBuffer.scala 359:111] + wire _io_deq_valid_T_5 = outputStateReg == 4'h7; // @[KvRingBuffer.scala 359:148] + wire _io_deq_valid_T_9 = outputStateReg == 4'ha; // @[KvRingBuffer.scala 359:232] + wire _io_deq_valid_T_11 = outputStateReg == 4'h9; // @[KvRingBuffer.scala 359:273] + wire _io_deq_valid_T_13 = outputStateReg == 4'hb; // @[KvRingBuffer.scala 359:312] + assign mem_data_en = 1'h1; // @[KvRingBuffer.scala 180:{24,24} 84:26] + `ifndef RANDOMIZE_GARBAGE_ASSIGN + assign mem_data_data = mem[mem_data_addr]; // @[KvRingBuffer.scala 84:26] + `else + assign mem_data_data = mem_data_addr >= 11'h500 ? _RAND_2[31:0] : mem[mem_data_addr]; // @[KvRingBuffer.scala 84:26] + `endif // RANDOMIZE_GARBAGE_ASSIGN + assign mem_MPORT_data = _writeDataPtr_T ? io_enq_bits : writeReg; // @[KvRingBuffer.scala 129:72] + assign mem_MPORT_addr = {{1'd0}, _T_4}; + assign mem_MPORT_mask = 1'h1; + assign mem_MPORT_en = 1'h1; + assign io_deq_valid = outputStateReg == 4'h4 | outputStateReg == 4'h6 | outputStateReg == 4'h5 | outputStateReg == 4'h7 + | outputStateReg == 4'h8 | outputStateReg == 4'ha | outputStateReg == 4'h9 | outputStateReg == 4'hb; // @[KvRingBuffer.scala 359:294] + assign io_deq_bits = _io_deq_valid_T_3 | _io_deq_valid_T_5 | _io_deq_valid_T_11 | _io_deq_valid_T_13 ? shadowReg : + mem_data_data; // @[KvRingBuffer.scala 360:23] + assign io_lastOutput = _io_deq_valid_T_9 | _io_deq_valid_T_13; // @[KvRingBuffer.scala 362:61] + assign io_metadataValid = outputStateReg == 4'h2 | outputStateReg == 4'h3; // @[KvRingBuffer.scala 366:61] + always @(posedge clock) begin + if (mem_data_en) begin + mem_data_addr <= {{1'd0}, readFullPtr}; // @[KvRingBuffer.scala 180:24] + end + if (mem_MPORT_en & mem_MPORT_mask) begin + mem[mem_MPORT_addr] <= mem_MPORT_data; // @[KvRingBuffer.scala 84:26] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readPtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrRead) begin // @[KvRingBuffer.scala 77:21] + if (readPtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + readPtr <= 2'h0; + end else begin + readPtr <= _nextVal_T_2; + end + end + if (reset) begin // @[KvRingBuffer.scala 122:33] + outputStateReg <= 4'h0; // @[KvRingBuffer.scala 122:33] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + outputStateReg <= 4'h1; // @[KvRingBuffer.scala 188:32] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h2; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h3; + end else begin + outputStateReg <= _GEN_163; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writePtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrWrite) begin // @[KvRingBuffer.scala 77:21] + if (writePtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + writePtr <= 2'h0; + end else begin + writePtr <= _nextVal_T_5; + end + end + if (reset) begin // @[KvRingBuffer.scala 121:32] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 121:32] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + inputStateReg <= _GEN_6; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h2; // @[KvRingBuffer.scala 154:27] + end else if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 165:27] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (io_isInputKey) begin // @[KvRingBuffer.scala 140:38] + writeKeyChunkPtr <= _nextVal_T_8; // @[KvRingBuffer.scala 141:38] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 166:30] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeValueChunkPtr <= _nextVal_T_11; // @[KvRingBuffer.scala 143:40] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 167:32] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 186:33] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h1; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h0; + end else begin + readKeyChunkPtr <= _GEN_162; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 187:35] + end + end else if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readValueChunkPtr <= 10'h2; + end else begin + readValueChunkPtr <= _GEN_161; + end + end + if (reset) begin // @[KvRingBuffer.scala 108:25] + keyLen <= 32'h0; // @[KvRingBuffer.scala 108:25] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + keyLen <= _GEN_48; + end + end + end + if (reset) begin // @[KvRingBuffer.scala 109:27] + valueLen <= 32'h0; // @[KvRingBuffer.scala 109:27] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + valueLen <= _GEN_160; + end + end + end + emptyReg <= reset | _GEN_188; // @[KvRingBuffer.scala 111:{27,27}] + if (reset) begin // @[KvRingBuffer.scala 112:26] + fullReg <= 1'h0; // @[KvRingBuffer.scala 112:26] + end else if (!(2'h0 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + fullReg <= nextWrite == readPtr; // @[KvRingBuffer.scala 162:21] + end + end + end + if (reset) begin // @[KvRingBuffer.scala 124:27] + writeReg <= 32'h0; // @[KvRingBuffer.scala 124:27] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeReg <= _GEN_7; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeReg <= {{22'd0}, writeValueChunkPtr}; // @[KvRingBuffer.scala 155:22] + end + if (reset) begin // @[KvRingBuffer.scala 181:28] + shadowReg <= 32'h0; // @[KvRingBuffer.scala 181:28] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + shadowReg <= _GEN_165; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_GARBAGE_ASSIGN + _RAND_2 = {1{`RANDOM}}; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 1280; initvar = initvar+1) + mem[initvar] = _RAND_0[31:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + mem_data_addr = _RAND_1[10:0]; + _RAND_3 = {1{`RANDOM}}; + readPtr = _RAND_3[1:0]; + _RAND_4 = {1{`RANDOM}}; + outputStateReg = _RAND_4[3:0]; + _RAND_5 = {1{`RANDOM}}; + writePtr = _RAND_5[1:0]; + _RAND_6 = {1{`RANDOM}}; + inputStateReg = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + writeKeyChunkPtr = _RAND_7[9:0]; + _RAND_8 = {1{`RANDOM}}; + writeValueChunkPtr = _RAND_8[9:0]; + _RAND_9 = {1{`RANDOM}}; + readKeyChunkPtr = _RAND_9[9:0]; + _RAND_10 = {1{`RANDOM}}; + readValueChunkPtr = _RAND_10[9:0]; + _RAND_11 = {1{`RANDOM}}; + keyLen = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + valueLen = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + emptyReg = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + fullReg = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + writeReg = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + shadowReg = _RAND_16[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummyKvPairFifo( + input clock, + input reset, + input [31:0] io_axi_s_tdata, + input io_axi_s_tvalid, + output io_axi_s_tready, + input io_axi_s_tlast, + output [31:0] io_axi_m_tdata, + output io_axi_m_tvalid, + input io_axi_m_tready, + output io_axi_m_tlast +); + wire encoder_clock; // @[DummyKvPairFifo.scala 16:25] + wire encoder_reset; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_valid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_input_deq_bits; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_lastOutput; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_metadataValid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tready; // @[DummyKvPairFifo.scala 16:25] + wire decoder_clock; // @[DummyKvPairFifo.scala 17:25] + wire decoder_reset; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_input_axi_s_tdata; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tvalid; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tready; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 17:25] + wire kvOutputBuffer_clock; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_reset; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_enq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_enq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastInput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_isInputKey; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_ready; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 18:32] + DummyEncoder encoder ( // @[DummyKvPairFifo.scala 16:25] + .clock(encoder_clock), + .reset(encoder_reset), + .io_input_deq_ready(encoder_io_input_deq_ready), + .io_input_deq_valid(encoder_io_input_deq_valid), + .io_input_deq_bits(encoder_io_input_deq_bits), + .io_input_lastOutput(encoder_io_input_lastOutput), + .io_input_metadataValid(encoder_io_input_metadataValid), + .io_output_axi_m_tdata(encoder_io_output_axi_m_tdata), + .io_output_axi_m_tvalid(encoder_io_output_axi_m_tvalid), + .io_output_axi_m_tready(encoder_io_output_axi_m_tready) + ); + DummyDecoder decoder ( // @[DummyKvPairFifo.scala 17:25] + .clock(decoder_clock), + .reset(decoder_reset), + .io_input_axi_s_tdata(decoder_io_input_axi_s_tdata), + .io_input_axi_s_tvalid(decoder_io_input_axi_s_tvalid), + .io_input_axi_s_tready(decoder_io_input_axi_s_tready), + .io_output_enq_valid(decoder_io_output_enq_valid), + .io_output_enq_bits(decoder_io_output_enq_bits), + .io_output_lastInput(decoder_io_output_lastInput), + .io_output_isInputKey(decoder_io_output_isInputKey) + ); + KVRingBuffer kvOutputBuffer ( // @[DummyKvPairFifo.scala 18:32] + .clock(kvOutputBuffer_clock), + .reset(kvOutputBuffer_reset), + .io_enq_valid(kvOutputBuffer_io_enq_valid), + .io_enq_bits(kvOutputBuffer_io_enq_bits), + .io_lastInput(kvOutputBuffer_io_lastInput), + .io_isInputKey(kvOutputBuffer_io_isInputKey), + .io_deq_ready(kvOutputBuffer_io_deq_ready), + .io_deq_valid(kvOutputBuffer_io_deq_valid), + .io_deq_bits(kvOutputBuffer_io_deq_bits), + .io_lastOutput(kvOutputBuffer_io_lastOutput), + .io_metadataValid(kvOutputBuffer_io_metadataValid) + ); + assign io_axi_s_tready = 1'h1; // @[DummyKvPairFifo.scala 33:28] + assign io_axi_m_tdata = encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tvalid = encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tlast = 1'h0; // @[DummyKvPairFifo.scala 32:29] + assign encoder_clock = clock; + assign encoder_reset = reset; + assign encoder_io_input_deq_valid = kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_deq_bits = kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_lastOutput = kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 28:33] + assign encoder_io_input_metadataValid = kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 29:36] + assign encoder_io_output_axi_m_tready = io_axi_m_tready; // @[DummyKvPairFifo.scala 32:29] + assign decoder_clock = clock; + assign decoder_reset = reset; + assign decoder_io_input_axi_s_tdata = io_axi_s_tdata; // @[DummyKvPairFifo.scala 33:28] + assign decoder_io_input_axi_s_tvalid = io_axi_s_tvalid; // @[DummyKvPairFifo.scala 33:28] + assign kvOutputBuffer_clock = clock; + assign kvOutputBuffer_reset = reset; + assign kvOutputBuffer_io_enq_valid = decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_enq_bits = decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_lastInput = decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 38:33] + assign kvOutputBuffer_io_isInputKey = decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 37:34] + assign kvOutputBuffer_io_deq_ready = encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 26:26] +endmodule diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/component.xml b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/component.xml new file mode 100644 index 0000000..8384a00 --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/component.xml @@ -0,0 +1,362 @@ + + + bme.hu + user + DummyKvPairFifo + 1.1 + + + reset + + + + + + + RST + + + reset + + + + + + clock + + + + + + + CLK + + + clock + + + + + + ASSOCIATED_RESET + reset + + + ASSOCIATED_BUSIF + axi_m:axis_s + + + FREQ_HZ + 100000000 + + + + + axis_s + + + + + + + TDATA + + + io_axi_s_tdata + + + + + TLAST + + + io_axi_s_tlast + + + + + TVALID + + + io_axi_s_tvalid + + + + + TREADY + + + io_axi_s_tready + + + + + + axi_m + + + + + + + TDATA + + + io_axi_m_tdata + + + + + TLAST + + + io_axi_m_tlast + + + + + TVALID + + + io_axi_m_tvalid + + + + + TREADY + + + io_axi_m_tready + + + + + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f64a5dae + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + DummyKvPairFifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 235b1c6c + + + + + + + clock + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_s_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + io_axi_s_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_s_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_s_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_m_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + + + + + + io_axi_m_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_m_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + + + + + + io_axi_m_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/DummyKvPairFifo_v1_1.tcl + tclSource + CHECKSUM_f64a5dae + XGUI_VERSION_2 + + + + xilinx_anylanguagesynthesis_view_fileset + + src/DummyKvPairFifo.v + verilogSource + CHECKSUM_235b1c6c + xil_defaultlib + + + + DummyKvPairFifo + + + Component_Name + inverter_v1_0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + zynquplus + + + /UserIP + + DummyKvPairFifo_v1_1 + package_project + 16 + 2023-10-25T17:09:38Z + + + 2022.1 + + + + + + + diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/inventer.v b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/inventer.v new file mode 100644 index 0000000..eeb076a --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/inventer.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 02/25/2020 01:13:15 PM +// Design Name: +// Module Name: inverter +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module inverter #(parameter DATA_WIDTH=32) + ( + input axi_clk, + input axi_reset_n, + //AXI4-S slave i/f + input s_axis_valid, + input [DATA_WIDTH-1:0] s_axis_data, + output s_axis_ready, + //AXI4-S master i/f + output reg m_axis_valid, + output reg [DATA_WIDTH-1:0] m_axis_data, + input m_axis_ready + ); + + integer i; + + assign s_axis_ready = m_axis_ready & cnt != 3; + + reg [1:0] cnt; + + always @(posedge axi_clk) + begin + if(s_axis_valid & s_axis_ready) + begin + for(i=0;i= 11'h500 ? _RAND_2[31:0] : mem[mem_data_addr]; // @[KvRingBuffer.scala 84:26] + `endif // RANDOMIZE_GARBAGE_ASSIGN + assign mem_MPORT_data = _writeDataPtr_T ? io_enq_bits : writeReg; // @[KvRingBuffer.scala 129:72] + assign mem_MPORT_addr = {{1'd0}, _T_4}; + assign mem_MPORT_mask = 1'h1; + assign mem_MPORT_en = 1'h1; + assign io_deq_valid = outputStateReg == 4'h4 | outputStateReg == 4'h6 | outputStateReg == 4'h5 | outputStateReg == 4'h7 + | outputStateReg == 4'h8 | outputStateReg == 4'ha | outputStateReg == 4'h9 | outputStateReg == 4'hb; // @[KvRingBuffer.scala 359:294] + assign io_deq_bits = _io_deq_valid_T_3 | _io_deq_valid_T_5 | _io_deq_valid_T_11 | _io_deq_valid_T_13 ? shadowReg : + mem_data_data; // @[KvRingBuffer.scala 360:23] + assign io_lastOutput = _io_deq_valid_T_9 | _io_deq_valid_T_13; // @[KvRingBuffer.scala 362:61] + assign io_metadataValid = outputStateReg == 4'h2 | outputStateReg == 4'h3; // @[KvRingBuffer.scala 366:61] + always @(posedge clock) begin + if (mem_data_en) begin + mem_data_addr <= {{1'd0}, readFullPtr}; // @[KvRingBuffer.scala 180:24] + end + if (mem_MPORT_en & mem_MPORT_mask) begin + mem[mem_MPORT_addr] <= mem_MPORT_data; // @[KvRingBuffer.scala 84:26] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readPtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrRead) begin // @[KvRingBuffer.scala 77:21] + if (readPtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + readPtr <= 2'h0; + end else begin + readPtr <= _nextVal_T_2; + end + end + if (reset) begin // @[KvRingBuffer.scala 122:33] + outputStateReg <= 4'h0; // @[KvRingBuffer.scala 122:33] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + outputStateReg <= 4'h1; // @[KvRingBuffer.scala 188:32] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h2; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h3; + end else begin + outputStateReg <= _GEN_163; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writePtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrWrite) begin // @[KvRingBuffer.scala 77:21] + if (writePtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + writePtr <= 2'h0; + end else begin + writePtr <= _nextVal_T_5; + end + end + if (reset) begin // @[KvRingBuffer.scala 121:32] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 121:32] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + inputStateReg <= _GEN_6; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h2; // @[KvRingBuffer.scala 154:27] + end else if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 165:27] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (io_isInputKey) begin // @[KvRingBuffer.scala 140:38] + writeKeyChunkPtr <= _nextVal_T_8; // @[KvRingBuffer.scala 141:38] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 166:30] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeValueChunkPtr <= _nextVal_T_11; // @[KvRingBuffer.scala 143:40] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 167:32] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 186:33] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h1; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h0; + end else begin + readKeyChunkPtr <= _GEN_162; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 187:35] + end + end else if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readValueChunkPtr <= 10'h2; + end else begin + readValueChunkPtr <= _GEN_161; + end + end + if (reset) begin // @[KvRingBuffer.scala 108:25] + keyLen <= 32'h0; // @[KvRingBuffer.scala 108:25] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + keyLen <= _GEN_48; + end + end + end + if (reset) begin // @[KvRingBuffer.scala 109:27] + valueLen <= 32'h0; // @[KvRingBuffer.scala 109:27] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + valueLen <= _GEN_160; + end + end + end + emptyReg <= reset | _GEN_188; // @[KvRingBuffer.scala 111:{27,27}] + if (reset) begin // @[KvRingBuffer.scala 112:26] + fullReg <= 1'h0; // @[KvRingBuffer.scala 112:26] + end else if (!(2'h0 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + fullReg <= nextWrite == readPtr; // @[KvRingBuffer.scala 162:21] + end + end + end + if (reset) begin // @[KvRingBuffer.scala 124:27] + writeReg <= 32'h0; // @[KvRingBuffer.scala 124:27] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeReg <= _GEN_7; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeReg <= {{22'd0}, writeValueChunkPtr}; // @[KvRingBuffer.scala 155:22] + end + if (reset) begin // @[KvRingBuffer.scala 181:28] + shadowReg <= 32'h0; // @[KvRingBuffer.scala 181:28] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + shadowReg <= _GEN_165; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_GARBAGE_ASSIGN + _RAND_2 = {1{`RANDOM}}; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 1280; initvar = initvar+1) + mem[initvar] = _RAND_0[31:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + mem_data_addr = _RAND_1[10:0]; + _RAND_3 = {1{`RANDOM}}; + readPtr = _RAND_3[1:0]; + _RAND_4 = {1{`RANDOM}}; + outputStateReg = _RAND_4[3:0]; + _RAND_5 = {1{`RANDOM}}; + writePtr = _RAND_5[1:0]; + _RAND_6 = {1{`RANDOM}}; + inputStateReg = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + writeKeyChunkPtr = _RAND_7[9:0]; + _RAND_8 = {1{`RANDOM}}; + writeValueChunkPtr = _RAND_8[9:0]; + _RAND_9 = {1{`RANDOM}}; + readKeyChunkPtr = _RAND_9[9:0]; + _RAND_10 = {1{`RANDOM}}; + readValueChunkPtr = _RAND_10[9:0]; + _RAND_11 = {1{`RANDOM}}; + keyLen = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + valueLen = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + emptyReg = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + fullReg = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + writeReg = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + shadowReg = _RAND_16[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummyKvPairFifo( + input clock, + input reset, + input [31:0] io_axi_s_tdata, + input io_axi_s_tvalid, + output io_axi_s_tready, + input io_axi_s_tlast, + output [31:0] io_axi_m_tdata, + output io_axi_m_tvalid, + input io_axi_m_tready, + output io_axi_m_tlast +); + wire encoder_clock; // @[DummyKvPairFifo.scala 16:25] + wire encoder_reset; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_valid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_input_deq_bits; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_lastOutput; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_metadataValid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tready; // @[DummyKvPairFifo.scala 16:25] + wire decoder_clock; // @[DummyKvPairFifo.scala 17:25] + wire decoder_reset; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_input_axi_s_tdata; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tvalid; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tready; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 17:25] + wire kvOutputBuffer_clock; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_reset; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_enq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_enq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastInput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_isInputKey; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_ready; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 18:32] + DummyEncoder encoder ( // @[DummyKvPairFifo.scala 16:25] + .clock(encoder_clock), + .reset(encoder_reset), + .io_input_deq_ready(encoder_io_input_deq_ready), + .io_input_deq_valid(encoder_io_input_deq_valid), + .io_input_deq_bits(encoder_io_input_deq_bits), + .io_input_lastOutput(encoder_io_input_lastOutput), + .io_input_metadataValid(encoder_io_input_metadataValid), + .io_output_axi_m_tdata(encoder_io_output_axi_m_tdata), + .io_output_axi_m_tvalid(encoder_io_output_axi_m_tvalid), + .io_output_axi_m_tready(encoder_io_output_axi_m_tready) + ); + DummyDecoder decoder ( // @[DummyKvPairFifo.scala 17:25] + .clock(decoder_clock), + .reset(decoder_reset), + .io_input_axi_s_tdata(decoder_io_input_axi_s_tdata), + .io_input_axi_s_tvalid(decoder_io_input_axi_s_tvalid), + .io_input_axi_s_tready(decoder_io_input_axi_s_tready), + .io_output_enq_valid(decoder_io_output_enq_valid), + .io_output_enq_bits(decoder_io_output_enq_bits), + .io_output_lastInput(decoder_io_output_lastInput), + .io_output_isInputKey(decoder_io_output_isInputKey) + ); + KVRingBuffer kvOutputBuffer ( // @[DummyKvPairFifo.scala 18:32] + .clock(kvOutputBuffer_clock), + .reset(kvOutputBuffer_reset), + .io_enq_valid(kvOutputBuffer_io_enq_valid), + .io_enq_bits(kvOutputBuffer_io_enq_bits), + .io_lastInput(kvOutputBuffer_io_lastInput), + .io_isInputKey(kvOutputBuffer_io_isInputKey), + .io_deq_ready(kvOutputBuffer_io_deq_ready), + .io_deq_valid(kvOutputBuffer_io_deq_valid), + .io_deq_bits(kvOutputBuffer_io_deq_bits), + .io_lastOutput(kvOutputBuffer_io_lastOutput), + .io_metadataValid(kvOutputBuffer_io_metadataValid) + ); + assign io_axi_s_tready = 1'h1; // @[DummyKvPairFifo.scala 33:28] + assign io_axi_m_tdata = encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tvalid = encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tlast = 1'h0; // @[DummyKvPairFifo.scala 32:29] + assign encoder_clock = clock; + assign encoder_reset = reset; + assign encoder_io_input_deq_valid = kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_deq_bits = kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_lastOutput = kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 28:33] + assign encoder_io_input_metadataValid = kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 29:36] + assign encoder_io_output_axi_m_tready = io_axi_m_tready; // @[DummyKvPairFifo.scala 32:29] + assign decoder_clock = clock; + assign decoder_reset = reset; + assign decoder_io_input_axi_s_tdata = io_axi_s_tdata; // @[DummyKvPairFifo.scala 33:28] + assign decoder_io_input_axi_s_tvalid = io_axi_s_tvalid; // @[DummyKvPairFifo.scala 33:28] + assign kvOutputBuffer_clock = clock; + assign kvOutputBuffer_reset = reset; + assign kvOutputBuffer_io_enq_valid = decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_enq_bits = decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_lastInput = decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 38:33] + assign kvOutputBuffer_io_isInputKey = decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 37:34] + assign kvOutputBuffer_io_deq_ready = encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 26:26] +endmodule diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_0.tcl b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_0.tcl new file mode 100644 index 0000000..0db18e9 --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_1.tcl b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_1.tcl new file mode 100644 index 0000000..0db18e9 --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/DummyKvPairFifo_v1_1.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/inverter_v1_0.tcl b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/inverter_v1_0.tcl new file mode 100644 index 0000000..55a2622 --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.srcs/sources_1/new/xgui/inverter_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/Vivado/ip_repo/CompactionUnit/CompactionUnit.xpr b/Vivado/ip_repo/CompactionUnit/CompactionUnit.xpr new file mode 100644 index 0000000..286bc9a --- /dev/null +++ b/Vivado/ip_repo/CompactionUnit/CompactionUnit.xpr @@ -0,0 +1,219 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/Vivado/src/hdl/DummyKvPairFifo.v b/Vivado/src/hdl/DummyKvPairFifo.v new file mode 100644 index 0000000..bf605ab --- /dev/null +++ b/Vivado/src/hdl/DummyKvPairFifo.v @@ -0,0 +1,755 @@ +module DummyEncoder( + input clock, + input reset, + output io_input_deq_ready, + input io_input_deq_valid, + input [31:0] io_input_deq_bits, + input io_input_lastOutput, + input io_input_metadataValid, + output [31:0] io_output_axi_m_tdata, + output io_output_axi_m_tvalid, + input io_output_axi_m_tready +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + reg [1:0] state; // @[DummyEncoder.scala 24:24] + reg [31:0] status; // @[DummyEncoder.scala 25:25] + wire [31:0] _status_T_3 = {status[31:16],io_input_deq_bits[7:0],status[7:0]}; // @[Cat.scala 33:92] + wire [31:0] _status_T_7 = {status[31:24],io_input_deq_bits[7:0],status[15:0]}; // @[Cat.scala 33:92] + wire [1:0] _GEN_3 = io_output_axi_m_tready ? 2'h3 : state; // @[DummyEncoder.scala 43:43 44:23 24:24] + wire [1:0] _GEN_4 = io_input_lastOutput & io_output_axi_m_tready ? 2'h0 : state; // @[DummyEncoder.scala 49:66 50:23 24:24] + wire [1:0] _GEN_5 = 2'h3 == state ? _GEN_4 : state; // @[DummyEncoder.scala 27:20 24:24] + wire _io_output_axi_m_tdata_T = state == 2'h2; // @[DummyEncoder.scala 56:40] + assign io_input_deq_ready = state == 2'h3 & io_output_axi_m_tready; // @[DummyEncoder.scala 55:48] + assign io_output_axi_m_tdata = state == 2'h2 ? status : io_input_deq_bits; // @[DummyEncoder.scala 56:33] + assign io_output_axi_m_tvalid = _io_output_axi_m_tdata_T | io_input_deq_valid; // @[DummyEncoder.scala 57:54] + always @(posedge clock) begin + if (reset) begin // @[DummyEncoder.scala 24:24] + state <= 2'h0; // @[DummyEncoder.scala 24:24] + end else if (2'h0 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 29:43] + state <= 2'h1; // @[DummyEncoder.scala 31:23] + end + end else if (2'h1 == state) begin // @[DummyEncoder.scala 27:20] + state <= 2'h2; // @[DummyEncoder.scala 39:19] + end else if (2'h2 == state) begin // @[DummyEncoder.scala 27:20] + state <= _GEN_3; + end else begin + state <= _GEN_5; + end + if (reset) begin // @[DummyEncoder.scala 25:25] + status <= 32'h0; // @[DummyEncoder.scala 25:25] + end else if (2'h0 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 29:43] + status <= _status_T_3; // @[DummyEncoder.scala 30:24] + end + end else if (2'h1 == state) begin // @[DummyEncoder.scala 27:20] + if (io_input_metadataValid) begin // @[DummyEncoder.scala 36:43] + status <= _status_T_7; // @[DummyEncoder.scala 37:24] + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + status = _RAND_1[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummyDecoder( + input clock, + input reset, + input [31:0] io_input_axi_s_tdata, + input io_input_axi_s_tvalid, + output io_input_axi_s_tready, + output io_output_enq_valid, + output [31:0] io_output_enq_bits, + output io_output_lastInput, + output io_output_isInputKey +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + reg [1:0] state; // @[DummyDecoder.scala 27:24] + reg [31:0] status; // @[DummyDecoder.scala 28:25] + reg [7:0] counter; // @[DummyDecoder.scala 32:26] + wire [7:0] keyLen = status[15:8] - 8'h1; // @[DummyDecoder.scala 35:32] + wire [7:0] valueLen = status[23:16] - 8'h1; // @[DummyDecoder.scala 36:35] + wire _T_2 = io_input_axi_s_tvalid & io_input_axi_s_tready; // @[DummyDecoder.scala 48:41] + wire [7:0] _counter_T_1 = counter + 8'h1; // @[DummyDecoder.scala 49:36] + wire [1:0] _GEN_2 = counter == keyLen ? 2'h2 : state; // @[DummyDecoder.scala 27:24 51:43 52:27] + wire [7:0] _GEN_3 = counter == keyLen ? 8'h0 : _counter_T_1; // @[DummyDecoder.scala 49:25 51:43 53:29] + wire _T_6 = counter == valueLen; // @[DummyDecoder.scala 62:31] + wire [1:0] _GEN_6 = counter == valueLen ? 2'h0 : state; // @[DummyDecoder.scala 27:24 62:45 63:27] + wire [7:0] _GEN_7 = counter == valueLen ? 8'h0 : _counter_T_1; // @[DummyDecoder.scala 60:25 62:45 64:29] + wire [7:0] _GEN_9 = _T_2 ? _GEN_7 : counter; // @[DummyDecoder.scala 32:26 59:67] + wire [1:0] _GEN_10 = _T_2 ? _GEN_6 : state; // @[DummyDecoder.scala 27:24 59:67] + wire _io_output_enq_valid_T_1 = state == 2'h2; // @[DummyDecoder.scala 75:56] + assign io_input_axi_s_tready = 1'h1; // @[DummyDecoder.scala 72:27] + assign io_output_enq_valid = (state == 2'h1 | state == 2'h2) & io_input_axi_s_tvalid; // @[DummyDecoder.scala 75:71] + assign io_output_enq_bits = io_input_axi_s_tdata; // @[DummyDecoder.scala 76:24] + assign io_output_lastInput = _io_output_enq_valid_T_1 & _T_6; // @[DummyDecoder.scala 78:48] + assign io_output_isInputKey = state == 2'h1; // @[DummyDecoder.scala 77:35] + always @(posedge clock) begin + if (reset) begin // @[DummyDecoder.scala 27:24] + state <= 2'h0; // @[DummyDecoder.scala 27:24] + end else if (2'h0 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid) begin // @[DummyDecoder.scala 41:42] + state <= 2'h1; // @[DummyDecoder.scala 42:23] + end + end else if (2'h1 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid & io_input_axi_s_tready) begin // @[DummyDecoder.scala 48:67] + state <= _GEN_2; + end + end else if (2'h2 == state) begin // @[DummyDecoder.scala 39:20] + state <= _GEN_10; + end + if (reset) begin // @[DummyDecoder.scala 28:25] + status <= 32'h0; // @[DummyDecoder.scala 28:25] + end else if (2'h0 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid) begin // @[DummyDecoder.scala 41:42] + status <= io_input_axi_s_tdata; // @[DummyDecoder.scala 43:24] + end + end + if (reset) begin // @[DummyDecoder.scala 32:26] + counter <= 8'h0; // @[DummyDecoder.scala 32:26] + end else if (!(2'h0 == state)) begin // @[DummyDecoder.scala 39:20] + if (2'h1 == state) begin // @[DummyDecoder.scala 39:20] + if (io_input_axi_s_tvalid & io_input_axi_s_tready) begin // @[DummyDecoder.scala 48:67] + counter <= _GEN_3; + end + end else if (2'h2 == state) begin // @[DummyDecoder.scala 39:20] + counter <= _GEN_9; + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + status = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + counter = _RAND_2[7:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module KVRingBuffer( + input clock, + input reset, + input io_enq_valid, + input [31:0] io_enq_bits, + input io_lastInput, + input io_isInputKey, + input io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits, + output io_lastOutput, + output io_metadataValid +); +`ifdef RANDOMIZE_GARBAGE_ASSIGN + reg [31:0] _RAND_2; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_MEM_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_1; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; +`endif // RANDOMIZE_REG_INIT + reg [31:0] mem [0:1279]; // @[KvRingBuffer.scala 84:26] + wire mem_data_en; // @[KvRingBuffer.scala 180:{24,24} 84:{26,26}] + reg [10:0] mem_data_addr; // @[KvRingBuffer.scala 84:26] + wire [31:0] mem_data_data; // @[KvRingBuffer.scala 84:26] + wire [31:0] mem_MPORT_data; // @[KvRingBuffer.scala 84:26 129:72] + wire [10:0] mem_MPORT_addr; // @[KvRingBuffer.scala 84:26] + wire mem_MPORT_mask; // @[KvRingBuffer.scala 84:26] + wire mem_MPORT_en; // @[KvRingBuffer.scala 84:26] + reg [1:0] readPtr; // @[KvRingBuffer.scala 75:29] + wire [1:0] _nextVal_T_2 = readPtr + 2'h1; // @[KvRingBuffer.scala 76:63] + wire [1:0] nextRead = readPtr == 2'h3 ? 2'h0 : _nextVal_T_2; // @[KvRingBuffer.scala 76:26] + reg [3:0] outputStateReg; // @[KvRingBuffer.scala 122:33] + wire _GEN_126 = 4'ha == outputStateReg ? io_deq_ready : 4'hb == outputStateReg & io_deq_ready; // @[KvRingBuffer.scala 183:28] + wire _GEN_131 = 4'h9 == outputStateReg ? 1'h0 : _GEN_126; // @[KvRingBuffer.scala 183:28] + wire _GEN_137 = 4'h8 == outputStateReg ? 1'h0 : _GEN_131; // @[KvRingBuffer.scala 183:28] + wire _GEN_142 = 4'h7 == outputStateReg ? 1'h0 : _GEN_137; // @[KvRingBuffer.scala 183:28] + wire _GEN_147 = 4'h6 == outputStateReg ? 1'h0 : _GEN_142; // @[KvRingBuffer.scala 183:28] + wire _GEN_153 = 4'h5 == outputStateReg ? 1'h0 : _GEN_147; // @[KvRingBuffer.scala 183:28] + wire _GEN_159 = 4'h4 == outputStateReg ? 1'h0 : _GEN_153; // @[KvRingBuffer.scala 183:28] + wire _GEN_166 = 4'h3 == outputStateReg ? 1'h0 : _GEN_159; // @[KvRingBuffer.scala 183:28] + wire _GEN_174 = 4'h2 == outputStateReg ? 1'h0 : _GEN_166; // @[KvRingBuffer.scala 183:28] + wire _GEN_182 = 4'h1 == outputStateReg ? 1'h0 : _GEN_174; // @[KvRingBuffer.scala 183:28] + wire incrRead = 4'h0 == outputStateReg ? 1'h0 : _GEN_182; // @[KvRingBuffer.scala 183:28] + reg [1:0] writePtr; // @[KvRingBuffer.scala 75:29] + wire [1:0] _nextVal_T_5 = writePtr + 2'h1; // @[KvRingBuffer.scala 76:63] + wire [1:0] nextWrite = writePtr == 2'h3 ? 2'h0 : _nextVal_T_5; // @[KvRingBuffer.scala 76:26] + reg [1:0] inputStateReg; // @[KvRingBuffer.scala 121:32] + wire _GEN_25 = 2'h1 == inputStateReg ? 1'h0 : 2'h2 == inputStateReg; // @[KvRingBuffer.scala 135:27] + wire incrWrite = 2'h0 == inputStateReg ? 1'h0 : _GEN_25; // @[KvRingBuffer.scala 135:27] + reg [9:0] writeKeyChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_8 = writeKeyChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] writeValueChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_11 = writeValueChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] readKeyChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_14 = readKeyChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [9:0] readValueChunkPtr; // @[KvRingBuffer.scala 75:29] + wire [9:0] _nextVal_T_17 = readValueChunkPtr + 10'h1; // @[KvRingBuffer.scala 76:63] + reg [31:0] keyLen; // @[KvRingBuffer.scala 108:25] + reg [31:0] valueLen; // @[KvRingBuffer.scala 109:27] + reg emptyReg; // @[KvRingBuffer.scala 111:27] + reg fullReg; // @[KvRingBuffer.scala 112:26] + reg [31:0] writeReg; // @[KvRingBuffer.scala 124:27] + wire _writeDataPtr_T = inputStateReg == 2'h0; // @[KvRingBuffer.scala 126:42] + wire [2:0] _writeDataPtr_T_1 = io_isInputKey ? 3'h2 : 3'h6; // @[KvRingBuffer.scala 126:60] + wire [9:0] _writeDataPtr_T_2 = io_isInputKey ? writeKeyChunkPtr : writeValueChunkPtr; // @[KvRingBuffer.scala 126:152] + wire [9:0] _GEN_191 = {{7'd0}, _writeDataPtr_T_1}; // @[KvRingBuffer.scala 126:147] + wire [9:0] _writeDataPtr_T_4 = _GEN_191 + _writeDataPtr_T_2; // @[KvRingBuffer.scala 126:147] + wire [9:0] writeDataPtr = inputStateReg == 2'h0 ? _writeDataPtr_T_4 : 10'h0; // @[KvRingBuffer.scala 126:27] + wire metadataOffsetPtr = inputStateReg == 2'h2; // @[KvRingBuffer.scala 127:47] + wire [5:0] _T = writePtr * 4'h8; // @[KvRingBuffer.scala 129:24] + wire [9:0] _GEN_192 = {{4'd0}, _T}; // @[KvRingBuffer.scala 129:33] + wire [9:0] _T_2 = _GEN_192 + writeDataPtr; // @[KvRingBuffer.scala 129:33] + wire [9:0] _GEN_193 = {{9'd0}, metadataOffsetPtr}; // @[KvRingBuffer.scala 129:48] + wire [9:0] _T_4 = _T_2 + _GEN_193; // @[KvRingBuffer.scala 129:48] + wire [1:0] _GEN_6 = io_lastInput ? 2'h1 : inputStateReg; // @[KvRingBuffer.scala 121:32 144:40 145:39] + wire [31:0] _GEN_7 = io_lastInput ? {{22'd0}, writeKeyChunkPtr} : writeReg; // @[KvRingBuffer.scala 124:27 144:40 146:34] + wire _GEN_16 = 2'h2 == inputStateReg ? 1'h0 : emptyReg; // @[KvRingBuffer.scala 135:27 160:22 111:27] + wire _GEN_24 = 2'h1 == inputStateReg ? emptyReg : _GEN_16; // @[KvRingBuffer.scala 111:27 135:27] + wire _GEN_33 = 2'h0 == inputStateReg ? emptyReg : _GEN_24; // @[KvRingBuffer.scala 111:27 135:27] + wire [5:0] _readFullPtr_T = readPtr * 4'h8; // @[KvRingBuffer.scala 179:31] + wire [9:0] _GEN_194 = {{4'd0}, _readFullPtr_T}; // @[KvRingBuffer.scala 179:40] + wire [9:0] _readFullPtr_T_2 = _GEN_194 + readValueChunkPtr; // @[KvRingBuffer.scala 179:40] + wire [9:0] readFullPtr = _readFullPtr_T_2 + readKeyChunkPtr; // @[KvRingBuffer.scala 179:60] + reg [31:0] shadowReg; // @[KvRingBuffer.scala 181:28] + wire [31:0] _GEN_48 = mem_data_data; // @[KvRingBuffer.scala 200:42 201:24 108:25] + wire [9:0] _GEN_52 = keyLen == 32'h1 ? 10'h0 : readValueChunkPtr; // @[KvRingBuffer.scala 213:38 215:39] + wire [2:0] _GEN_53 = keyLen == 32'h1 ? 3'h6 : 3'h1; // @[KvRingBuffer.scala 213:38 216:37 221:37] + wire [3:0] _GEN_54 = keyLen == 32'h1 ? 4'h6 : 4'h4; // @[KvRingBuffer.scala 213:38 218:36 222:36] + wire [9:0] _GEN_56 = {{7'd0}, _GEN_53}; // @[KvRingBuffer.scala 212:42] + wire [31:0] _T_26 = keyLen - 32'h1; // @[KvRingBuffer.scala 230:54] + wire [31:0] _GEN_195 = {{22'd0}, readKeyChunkPtr}; // @[KvRingBuffer.scala 230:43] + wire _T_27 = _GEN_195 == _T_26; // @[KvRingBuffer.scala 230:43] + wire _emptyReg_T = nextRead == writePtr; // @[KvRingBuffer.scala 232:46] + wire [3:0] _GEN_58 = _GEN_195 == _T_26 ? 4'h6 : outputStateReg; // @[KvRingBuffer.scala 230:61 231:40] + wire _GEN_59 = _GEN_195 == _T_26 ? nextRead == writePtr : _GEN_33; // @[KvRingBuffer.scala 230:61 232:34] + wire [9:0] _GEN_60 = _GEN_195 == _T_26 ? 10'h0 : readValueChunkPtr; // @[KvRingBuffer.scala 230:61 233:43] + wire [9:0] _GEN_61 = _GEN_195 == _T_26 ? 10'h6 : _nextVal_T_14; // @[KvRingBuffer.scala 230:61 234:41 236:41] + wire [3:0] _GEN_62 = io_deq_ready ? _GEN_58 : 4'h5; // @[KvRingBuffer.scala 229:36 241:36] + wire _GEN_63 = io_deq_ready ? _GEN_59 : _GEN_33; // @[KvRingBuffer.scala 229:36] + wire [9:0] _GEN_64 = io_deq_ready ? _GEN_60 : readValueChunkPtr; // @[KvRingBuffer.scala 229:36] + wire [9:0] _GEN_65 = io_deq_ready ? _GEN_61 : readKeyChunkPtr; // @[KvRingBuffer.scala 229:36] + wire [31:0] _GEN_66 = io_deq_ready ? shadowReg : mem_data_data; // @[KvRingBuffer.scala 181:28 229:36 240:31] + wire [3:0] _GEN_72 = _T_27 ? 4'h6 : 4'h4; // @[KvRingBuffer.scala 248:57 249:36 254:36] + wire [3:0] _GEN_76 = io_deq_ready ? _GEN_72 : outputStateReg; // @[KvRingBuffer.scala 247:57] + wire [3:0] _GEN_80 = valueLen == 32'h1 ? 4'ha : 4'h8; // @[KvRingBuffer.scala 266:48 267:44 269:44] + wire [9:0] _GEN_81 = valueLen == 32'h1 ? readValueChunkPtr : 10'h1; // @[KvRingBuffer.scala 266:48 270:47] + wire [3:0] _GEN_84 = io_deq_ready ? _GEN_80 : 4'h7; // @[KvRingBuffer.scala 262:36 275:36] + wire [9:0] _GEN_85 = io_deq_ready ? _GEN_81 : readValueChunkPtr; // @[KvRingBuffer.scala 262:36] + wire [3:0] _GEN_93 = io_deq_ready ? _GEN_80 : outputStateReg; // @[KvRingBuffer.scala 281:57] + wire [31:0] _T_44 = valueLen - 32'h1; // @[KvRingBuffer.scala 298:57] + wire [31:0] _GEN_197 = {{22'd0}, readValueChunkPtr}; // @[KvRingBuffer.scala 298:44] + wire _T_45 = _GEN_197 == _T_44; // @[KvRingBuffer.scala 298:44] + wire [3:0] _GEN_95 = _GEN_197 == _T_44 ? 4'ha : outputStateReg; // @[KvRingBuffer.scala 298:64 299:40] + wire _GEN_96 = _GEN_197 == _T_44 ? _emptyReg_T : _GEN_33; // @[KvRingBuffer.scala 298:64 303:34] + wire [9:0] _GEN_97 = _GEN_197 == _T_44 ? readValueChunkPtr : _nextVal_T_17; // @[KvRingBuffer.scala 298:64 305:43] + wire [3:0] _GEN_98 = io_deq_ready ? _GEN_95 : 4'h9; // @[KvRingBuffer.scala 297:36 310:36] + wire _GEN_99 = io_deq_ready ? _GEN_96 : _GEN_33; // @[KvRingBuffer.scala 297:36] + wire [9:0] _GEN_100 = io_deq_ready ? _GEN_97 : readValueChunkPtr; // @[KvRingBuffer.scala 297:36] + wire [3:0] _GEN_105 = _T_45 ? 4'ha : 4'h8; // @[KvRingBuffer.scala 317:60 318:36 324:36] + wire [3:0] _GEN_108 = io_deq_ready ? _GEN_105 : outputStateReg; // @[KvRingBuffer.scala 316:57] + wire [3:0] _GEN_111 = io_deq_ready ? 4'h0 : 4'hb; // @[KvRingBuffer.scala 332:36 333:36 341:36] + wire _GEN_112 = io_deq_ready ? _emptyReg_T : _GEN_33; // @[KvRingBuffer.scala 332:36 334:30] + wire [3:0] _GEN_118 = io_deq_ready ? 4'h0 : outputStateReg; // @[KvRingBuffer.scala 347:57 348:32] + wire [3:0] _GEN_121 = 4'hb == outputStateReg ? _GEN_118 : outputStateReg; // @[KvRingBuffer.scala 183:28] + wire _GEN_122 = 4'hb == outputStateReg ? _GEN_112 : _GEN_33; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_124 = 4'ha == outputStateReg ? _GEN_111 : _GEN_121; // @[KvRingBuffer.scala 183:28] + wire _GEN_125 = 4'ha == outputStateReg ? _GEN_112 : _GEN_122; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_127 = 4'ha == outputStateReg ? _GEN_66 : shadowReg; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_128 = 4'h9 == outputStateReg ? _GEN_108 : _GEN_124; // @[KvRingBuffer.scala 183:28] + wire _GEN_129 = 4'h9 == outputStateReg ? _GEN_99 : _GEN_125; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_130 = 4'h9 == outputStateReg ? _GEN_100 : readValueChunkPtr; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_132 = 4'h9 == outputStateReg ? shadowReg : _GEN_127; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_133 = 4'h8 == outputStateReg ? _GEN_98 : _GEN_128; // @[KvRingBuffer.scala 183:28] + wire _GEN_134 = 4'h8 == outputStateReg ? _GEN_99 : _GEN_129; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_135 = 4'h8 == outputStateReg ? _GEN_100 : _GEN_130; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_136 = 4'h8 == outputStateReg ? _GEN_66 : _GEN_132; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_138 = 4'h7 == outputStateReg ? _GEN_93 : _GEN_133; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_139 = 4'h7 == outputStateReg ? _GEN_85 : _GEN_135; // @[KvRingBuffer.scala 183:28] + wire _GEN_140 = 4'h7 == outputStateReg ? _GEN_33 : _GEN_134; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_141 = 4'h7 == outputStateReg ? shadowReg : _GEN_136; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_143 = 4'h6 == outputStateReg ? _GEN_84 : _GEN_138; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_144 = 4'h6 == outputStateReg ? _GEN_85 : _GEN_139; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_145 = 4'h6 == outputStateReg ? _GEN_66 : _GEN_141; // @[KvRingBuffer.scala 183:28] + wire _GEN_146 = 4'h6 == outputStateReg ? _GEN_33 : _GEN_140; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_148 = 4'h5 == outputStateReg ? _GEN_76 : _GEN_143; // @[KvRingBuffer.scala 183:28] + wire _GEN_149 = 4'h5 == outputStateReg ? _GEN_63 : _GEN_146; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_150 = 4'h5 == outputStateReg ? _GEN_64 : _GEN_144; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_151 = 4'h5 == outputStateReg ? _GEN_65 : readKeyChunkPtr; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_152 = 4'h5 == outputStateReg ? shadowReg : _GEN_145; // @[KvRingBuffer.scala 181:28 183:28] + wire [3:0] _GEN_154 = 4'h4 == outputStateReg ? _GEN_62 : _GEN_148; // @[KvRingBuffer.scala 183:28] + wire _GEN_155 = 4'h4 == outputStateReg ? _GEN_63 : _GEN_149; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_156 = 4'h4 == outputStateReg ? _GEN_64 : _GEN_150; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_157 = 4'h4 == outputStateReg ? _GEN_65 : _GEN_151; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_158 = 4'h4 == outputStateReg ? _GEN_66 : _GEN_152; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_160 = 4'h3 == outputStateReg ? mem_data_data : valueLen; // @[KvRingBuffer.scala 183:28 211:22 109:27] + wire [9:0] _GEN_161 = 4'h3 == outputStateReg ? _GEN_52 : _GEN_156; // @[KvRingBuffer.scala 183:28] + wire [9:0] _GEN_162 = 4'h3 == outputStateReg ? _GEN_56 : _GEN_157; // @[KvRingBuffer.scala 183:28] + wire [3:0] _GEN_163 = 4'h3 == outputStateReg ? _GEN_54 : _GEN_154; // @[KvRingBuffer.scala 183:28] + wire _GEN_164 = 4'h3 == outputStateReg ? _GEN_33 : _GEN_155; // @[KvRingBuffer.scala 183:28] + wire [31:0] _GEN_165 = 4'h3 == outputStateReg ? shadowReg : _GEN_158; // @[KvRingBuffer.scala 181:28 183:28] + wire _GEN_172 = 4'h2 == outputStateReg ? _GEN_33 : _GEN_164; // @[KvRingBuffer.scala 183:28] + wire _GEN_180 = 4'h1 == outputStateReg ? _GEN_33 : _GEN_172; // @[KvRingBuffer.scala 183:28] + wire _GEN_188 = 4'h0 == outputStateReg ? _GEN_33 : _GEN_180; // @[KvRingBuffer.scala 183:28] + wire _io_deq_valid_T_3 = outputStateReg == 4'h5; // @[KvRingBuffer.scala 359:111] + wire _io_deq_valid_T_5 = outputStateReg == 4'h7; // @[KvRingBuffer.scala 359:148] + wire _io_deq_valid_T_9 = outputStateReg == 4'ha; // @[KvRingBuffer.scala 359:232] + wire _io_deq_valid_T_11 = outputStateReg == 4'h9; // @[KvRingBuffer.scala 359:273] + wire _io_deq_valid_T_13 = outputStateReg == 4'hb; // @[KvRingBuffer.scala 359:312] + assign mem_data_en = 1'h1; // @[KvRingBuffer.scala 180:{24,24} 84:26] + `ifndef RANDOMIZE_GARBAGE_ASSIGN + assign mem_data_data = mem[mem_data_addr]; // @[KvRingBuffer.scala 84:26] + `else + assign mem_data_data = mem_data_addr >= 11'h500 ? _RAND_2[31:0] : mem[mem_data_addr]; // @[KvRingBuffer.scala 84:26] + `endif // RANDOMIZE_GARBAGE_ASSIGN + assign mem_MPORT_data = _writeDataPtr_T ? io_enq_bits : writeReg; // @[KvRingBuffer.scala 129:72] + assign mem_MPORT_addr = {{1'd0}, _T_4}; + assign mem_MPORT_mask = 1'h1; + assign mem_MPORT_en = 1'h1; + assign io_deq_valid = outputStateReg == 4'h4 | outputStateReg == 4'h6 | outputStateReg == 4'h5 | outputStateReg == 4'h7 + | outputStateReg == 4'h8 | outputStateReg == 4'ha | outputStateReg == 4'h9 | outputStateReg == 4'hb; // @[KvRingBuffer.scala 359:294] + assign io_deq_bits = _io_deq_valid_T_3 | _io_deq_valid_T_5 | _io_deq_valid_T_11 | _io_deq_valid_T_13 ? shadowReg : + mem_data_data; // @[KvRingBuffer.scala 360:23] + assign io_lastOutput = _io_deq_valid_T_9 | _io_deq_valid_T_13; // @[KvRingBuffer.scala 362:61] + assign io_metadataValid = outputStateReg == 4'h2 | outputStateReg == 4'h3; // @[KvRingBuffer.scala 366:61] + always @(posedge clock) begin + if (mem_data_en) begin + mem_data_addr <= {{1'd0}, readFullPtr}; // @[KvRingBuffer.scala 180:24] + end + if (mem_MPORT_en & mem_MPORT_mask) begin + mem[mem_MPORT_addr] <= mem_MPORT_data; // @[KvRingBuffer.scala 84:26] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readPtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrRead) begin // @[KvRingBuffer.scala 77:21] + if (readPtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + readPtr <= 2'h0; + end else begin + readPtr <= _nextVal_T_2; + end + end + if (reset) begin // @[KvRingBuffer.scala 122:33] + outputStateReg <= 4'h0; // @[KvRingBuffer.scala 122:33] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + outputStateReg <= 4'h1; // @[KvRingBuffer.scala 188:32] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h2; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + outputStateReg <= 4'h3; + end else begin + outputStateReg <= _GEN_163; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writePtr <= 2'h0; // @[KvRingBuffer.scala 75:29] + end else if (incrWrite) begin // @[KvRingBuffer.scala 77:21] + if (writePtr == 2'h3) begin // @[KvRingBuffer.scala 76:26] + writePtr <= 2'h0; + end else begin + writePtr <= _nextVal_T_5; + end + end + if (reset) begin // @[KvRingBuffer.scala 121:32] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 121:32] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + inputStateReg <= _GEN_6; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h2; // @[KvRingBuffer.scala 154:27] + end else if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + inputStateReg <= 2'h0; // @[KvRingBuffer.scala 165:27] + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (io_isInputKey) begin // @[KvRingBuffer.scala 140:38] + writeKeyChunkPtr <= _nextVal_T_8; // @[KvRingBuffer.scala 141:38] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 166:30] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeValueChunkPtr <= _nextVal_T_11; // @[KvRingBuffer.scala 143:40] + end + end + end else if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 167:32] + end + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readKeyChunkPtr <= 10'h0; // @[KvRingBuffer.scala 186:33] + end + end else if (4'h1 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h1; + end else if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readKeyChunkPtr <= 10'h0; + end else begin + readKeyChunkPtr <= _GEN_162; + end + if (reset) begin // @[KvRingBuffer.scala 75:29] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 75:29] + end else if (4'h0 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + if (~emptyReg) begin // @[KvRingBuffer.scala 185:54] + readValueChunkPtr <= 10'h0; // @[KvRingBuffer.scala 187:35] + end + end else if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + readValueChunkPtr <= 10'h2; + end else begin + readValueChunkPtr <= _GEN_161; + end + end + if (reset) begin // @[KvRingBuffer.scala 108:25] + keyLen <= 32'h0; // @[KvRingBuffer.scala 108:25] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (4'h2 == outputStateReg) begin // @[KvRingBuffer.scala 183:28] + keyLen <= _GEN_48; + end + end + end + if (reset) begin // @[KvRingBuffer.scala 109:27] + valueLen <= 32'h0; // @[KvRingBuffer.scala 109:27] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + valueLen <= _GEN_160; + end + end + end + emptyReg <= reset | _GEN_188; // @[KvRingBuffer.scala 111:{27,27}] + if (reset) begin // @[KvRingBuffer.scala 112:26] + fullReg <= 1'h0; // @[KvRingBuffer.scala 112:26] + end else if (!(2'h0 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (!(2'h1 == inputStateReg)) begin // @[KvRingBuffer.scala 135:27] + if (2'h2 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + fullReg <= nextWrite == readPtr; // @[KvRingBuffer.scala 162:21] + end + end + end + if (reset) begin // @[KvRingBuffer.scala 124:27] + writeReg <= 32'h0; // @[KvRingBuffer.scala 124:27] + end else if (2'h0 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + if (io_enq_valid & ~fullReg) begin // @[KvRingBuffer.scala 137:44] + if (!(io_isInputKey)) begin // @[KvRingBuffer.scala 140:38] + writeReg <= _GEN_7; + end + end + end else if (2'h1 == inputStateReg) begin // @[KvRingBuffer.scala 135:27] + writeReg <= {{22'd0}, writeValueChunkPtr}; // @[KvRingBuffer.scala 155:22] + end + if (reset) begin // @[KvRingBuffer.scala 181:28] + shadowReg <= 32'h0; // @[KvRingBuffer.scala 181:28] + end else if (!(4'h0 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h1 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + if (!(4'h2 == outputStateReg)) begin // @[KvRingBuffer.scala 183:28] + shadowReg <= _GEN_165; + end + end + end + end +// Register and memory initialization +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_GARBAGE_ASSIGN + _RAND_2 = {1{`RANDOM}}; +`endif // RANDOMIZE_GARBAGE_ASSIGN +`ifdef RANDOMIZE_MEM_INIT + _RAND_0 = {1{`RANDOM}}; + for (initvar = 0; initvar < 1280; initvar = initvar+1) + mem[initvar] = _RAND_0[31:0]; +`endif // RANDOMIZE_MEM_INIT +`ifdef RANDOMIZE_REG_INIT + _RAND_1 = {1{`RANDOM}}; + mem_data_addr = _RAND_1[10:0]; + _RAND_3 = {1{`RANDOM}}; + readPtr = _RAND_3[1:0]; + _RAND_4 = {1{`RANDOM}}; + outputStateReg = _RAND_4[3:0]; + _RAND_5 = {1{`RANDOM}}; + writePtr = _RAND_5[1:0]; + _RAND_6 = {1{`RANDOM}}; + inputStateReg = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + writeKeyChunkPtr = _RAND_7[9:0]; + _RAND_8 = {1{`RANDOM}}; + writeValueChunkPtr = _RAND_8[9:0]; + _RAND_9 = {1{`RANDOM}}; + readKeyChunkPtr = _RAND_9[9:0]; + _RAND_10 = {1{`RANDOM}}; + readValueChunkPtr = _RAND_10[9:0]; + _RAND_11 = {1{`RANDOM}}; + keyLen = _RAND_11[31:0]; + _RAND_12 = {1{`RANDOM}}; + valueLen = _RAND_12[31:0]; + _RAND_13 = {1{`RANDOM}}; + emptyReg = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + fullReg = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + writeReg = _RAND_15[31:0]; + _RAND_16 = {1{`RANDOM}}; + shadowReg = _RAND_16[31:0]; +`endif // RANDOMIZE_REG_INIT + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS +endmodule +module DummyKvPairFifo( + input clock, + input reset, + input [31:0] io_axi_s_tdata, + input io_axi_s_tvalid, + output io_axi_s_tready, + input io_axi_s_tlast, + output [31:0] io_axi_m_tdata, + output io_axi_m_tvalid, + input io_axi_m_tready, + output io_axi_m_tlast +); + wire encoder_clock; // @[DummyKvPairFifo.scala 16:25] + wire encoder_reset; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_deq_valid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_input_deq_bits; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_lastOutput; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_input_metadataValid; // @[DummyKvPairFifo.scala 16:25] + wire [31:0] encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 16:25] + wire encoder_io_output_axi_m_tready; // @[DummyKvPairFifo.scala 16:25] + wire decoder_clock; // @[DummyKvPairFifo.scala 17:25] + wire decoder_reset; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_input_axi_s_tdata; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tvalid; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_input_axi_s_tready; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 17:25] + wire [31:0] decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 17:25] + wire decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 17:25] + wire kvOutputBuffer_clock; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_reset; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_enq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_enq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastInput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_isInputKey; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_ready; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 18:32] + wire [31:0] kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 18:32] + wire kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 18:32] + DummyEncoder encoder ( // @[DummyKvPairFifo.scala 16:25] + .clock(encoder_clock), + .reset(encoder_reset), + .io_input_deq_ready(encoder_io_input_deq_ready), + .io_input_deq_valid(encoder_io_input_deq_valid), + .io_input_deq_bits(encoder_io_input_deq_bits), + .io_input_lastOutput(encoder_io_input_lastOutput), + .io_input_metadataValid(encoder_io_input_metadataValid), + .io_output_axi_m_tdata(encoder_io_output_axi_m_tdata), + .io_output_axi_m_tvalid(encoder_io_output_axi_m_tvalid), + .io_output_axi_m_tready(encoder_io_output_axi_m_tready) + ); + DummyDecoder decoder ( // @[DummyKvPairFifo.scala 17:25] + .clock(decoder_clock), + .reset(decoder_reset), + .io_input_axi_s_tdata(decoder_io_input_axi_s_tdata), + .io_input_axi_s_tvalid(decoder_io_input_axi_s_tvalid), + .io_input_axi_s_tready(decoder_io_input_axi_s_tready), + .io_output_enq_valid(decoder_io_output_enq_valid), + .io_output_enq_bits(decoder_io_output_enq_bits), + .io_output_lastInput(decoder_io_output_lastInput), + .io_output_isInputKey(decoder_io_output_isInputKey) + ); + KVRingBuffer kvOutputBuffer ( // @[DummyKvPairFifo.scala 18:32] + .clock(kvOutputBuffer_clock), + .reset(kvOutputBuffer_reset), + .io_enq_valid(kvOutputBuffer_io_enq_valid), + .io_enq_bits(kvOutputBuffer_io_enq_bits), + .io_lastInput(kvOutputBuffer_io_lastInput), + .io_isInputKey(kvOutputBuffer_io_isInputKey), + .io_deq_ready(kvOutputBuffer_io_deq_ready), + .io_deq_valid(kvOutputBuffer_io_deq_valid), + .io_deq_bits(kvOutputBuffer_io_deq_bits), + .io_lastOutput(kvOutputBuffer_io_lastOutput), + .io_metadataValid(kvOutputBuffer_io_metadataValid) + ); + assign io_axi_s_tready = 1'h1; // @[DummyKvPairFifo.scala 33:28] + assign io_axi_m_tdata = encoder_io_output_axi_m_tdata; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tvalid = encoder_io_output_axi_m_tvalid; // @[DummyKvPairFifo.scala 32:29] + assign io_axi_m_tlast = 1'h0; // @[DummyKvPairFifo.scala 32:29] + assign encoder_clock = clock; + assign encoder_reset = reset; + assign encoder_io_input_deq_valid = kvOutputBuffer_io_deq_valid; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_deq_bits = kvOutputBuffer_io_deq_bits; // @[DummyKvPairFifo.scala 26:26] + assign encoder_io_input_lastOutput = kvOutputBuffer_io_lastOutput; // @[DummyKvPairFifo.scala 28:33] + assign encoder_io_input_metadataValid = kvOutputBuffer_io_metadataValid; // @[DummyKvPairFifo.scala 29:36] + assign encoder_io_output_axi_m_tready = io_axi_m_tready; // @[DummyKvPairFifo.scala 32:29] + assign decoder_clock = clock; + assign decoder_reset = reset; + assign decoder_io_input_axi_s_tdata = io_axi_s_tdata; // @[DummyKvPairFifo.scala 33:28] + assign decoder_io_input_axi_s_tvalid = io_axi_s_tvalid; // @[DummyKvPairFifo.scala 33:28] + assign kvOutputBuffer_clock = clock; + assign kvOutputBuffer_reset = reset; + assign kvOutputBuffer_io_enq_valid = decoder_io_output_enq_valid; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_enq_bits = decoder_io_output_enq_bits; // @[DummyKvPairFifo.scala 36:27] + assign kvOutputBuffer_io_lastInput = decoder_io_output_lastInput; // @[DummyKvPairFifo.scala 38:33] + assign kvOutputBuffer_io_isInputKey = decoder_io_output_isInputKey; // @[DummyKvPairFifo.scala 37:34] + assign kvOutputBuffer_io_deq_ready = encoder_io_input_deq_ready; // @[DummyKvPairFifo.scala 26:26] +endmodule diff --git a/Vivado/src/hdl/mysupercool.v b/Vivado/src/hdl/mysupercool.v new file mode 100644 index 0000000..3005c62 --- /dev/null +++ b/Vivado/src/hdl/mysupercool.v @@ -0,0 +1,71 @@ +module injector #(parameter DATA_WIDTH=32) + + ( + + input axi_clk, + + input axi_reset_n, + + //AXI4-S slave i/f + + input s_axis_valid, + + input [DATA_WIDTH-1:0] s_axis_data, + + output s_axis_ready, + + //AXI4-S master i/f + + output reg m_axis_valid, + + output reg [DATA_WIDTH-1:0] m_axis_data, + + input m_axis_ready + + ); + + + + integer i; + + + + assign s_axis_ready = m_axis_ready; + + + + always @(posedge axi_clk) + + begin + + if(s_axis_valid & s_axis_ready) + + begin + + for(i=0;i + + + + + + + + + + + + + + + + + + + + + + + active + 2 + PM + + + dmaSuperSystem + BC + + + 2 + dmaSuperSystem + VR + + + 0x00000000 + C_BASEADDR + 0x1FFFFFFF + C_HIGHADDR + Data_S2MM + /axi_dma_0 + M_AXI_S2MM + SEG_processing_system7_0_HP0_DDR_LOWOCM + xilinx.com:ip:axi_dma:7.1 + both + /processing_system7_0 + S_AXI_HP0 + HP0_DDR_LOWOCM + xilinx.com:ip:processing_system7:5.5 + memory + AC + + + 0x40400000 + C_BASEADDR + 0x4040FFFF + C_HIGHADDR + Data + /processing_system7_0 + M_AXI_GP0 + SEG_axi_dma_0_Reg + xilinx.com:ip:processing_system7:5.5 + both + /axi_dma_0 + S_AXI_LITE + Reg + xilinx.com:ip:axi_dma:7.1 + register + AC + + + 0x00000000 + C_BASEADDR + 0x1FFFFFFF + C_HIGHADDR + Data_MM2S + /axi_dma_0 + M_AXI_MM2S + SEG_processing_system7_0_HP0_DDR_LOWOCM + xilinx.com:ip:axi_dma:7.1 + both + /processing_system7_0 + S_AXI_HP0 + HP0_DDR_LOWOCM + xilinx.com:ip:processing_system7:5.5 + memory + AC + + + + + 2 + + + 2 + + + 2 + + + diff --git a/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_0/dmaSuperSystem_auto_pc_0.xci b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_0/dmaSuperSystem_auto_pc_0.xci new file mode 100644 index 0000000..789e634 --- /dev/null +++ b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_0/dmaSuperSystem_auto_pc_0.xci @@ -0,0 +1,461 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dmaSuperSystem_auto_pc_0 + + + S_AXI:M_AXI + + ARESETN + dmaSuperSystem_processing_system7_0_0_FCLK_CLK0 + 100000000 + 0 + 0 + 0.0 + 32 + 0 + 0 + 0 + dmaSuperSystem_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 8 + 4 + 8 + 4 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + ACTIVE_LOW + INTERCONNECT + 32 + 0 + 0 + 0 + dmaSuperSystem_processing_system7_0_0_FCLK_CLK0 + 32 + 100000000 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 12 + 0 + 16 + 8 + 4 + 8 + 4 + 0.0 + AXI3 + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 32 + 1 + 1 + 1 + 32 + 12 + 1 + 1 + 0 + 1 + 1 + zynq + 0 + 2 + 1 + 2 + 32 + 0 + 0 + 0 + dmaSuperSystem_auto_pc_0 + 32 + 12 + AXI4LITE + READ_WRITE + 0 + AXI3 + 2 + 0 + zynq + + + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 26 + TRUE + ../../../../../../LSM-Compactron3000.gen/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_0 + rtl + ../../ipshared + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_1/dmaSuperSystem_auto_pc_1.xci b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ip/dmaSuperSystem_auto_pc_1/dmaSuperSystem_auto_pc_1.xci new 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b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.srcs/sources_1/bd/dmaSuperSystem/ui/bd_ac33bd72.ui @@ -0,0 +1,37 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"0.610779", + "Default View_TopLeft":"169,-61", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.0r6 2020-01-29 bk=1.5227 VDI=41 GEI=36 GUI=JA:10.0 non-TLS +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 7 -x 2150 -y 400 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 7 -x 2150 -y 420 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 5 -x 1660 -y 440 -defaultsOSRD +preplace inst inverter_0 -pg 1 -lvl 2 -x 540 -y 110 -defaultsOSRD +preplace inst axi_dma_0 -pg 1 -lvl 3 -x 910 -y 140 -defaultsOSRD +preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -x 540 -y 470 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -x 200 -y 460 -defaultsOSRD +preplace inst axi_mem_intercon -pg 1 -lvl 4 -x 1270 -y 170 -defaultsOSRD +preplace inst system_ila_0 -pg 1 -lvl 6 -x 2030 -y 120 -defaultsOSRD +preplace netloc processing_system7_0_FCLK_CLK0 1 0 6 30 360 370 30 680 260 1080 350 1410 540 1890 +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 6 20 340 NJ 340 NJ 340 NJ 340 NJ 340 1860 +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 5 380 190 690 270 1090 330 N 330 1900 +preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 5 380 10 NJ 10 1070 10 N 10 1900 +preplace netloc axi_dma_0_M_AXI_MM2S 1 3 1 N 80 +preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 N 100 +preplace netloc axi_mem_intercon_M00_AXI 1 4 1 1420 170n +preplace netloc inverter_0_m_axis 1 2 4 700 320 N 320 N 320 1880 +preplace netloc processing_system7_0_DDR 1 5 2 NJ 400 N +preplace netloc processing_system7_0_FIXED_IO 1 5 2 NJ 420 N +preplace netloc processing_system7_0_M_AXI_GP0 1 1 5 390 20 NJ 20 NJ 20 NJ 20 1870 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 710 90n +levelinfo -pg 1 0 200 540 910 1270 1660 2030 2150 +pagesize -pg 1 -db -bbox -sgen 0 0 2260 590 +" +} +{ + "da_axi4_cnt":"4", + "da_clkrst_cnt":"1", + "da_ps7_cnt":"1" +} diff --git a/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.xpr b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.xpr new file mode 100644 index 0000000..689bd5a --- /dev/null +++ b/Vivado_old/LSM-Compactron3000/LSM-Compactron3000.xpr @@ -0,0 +1,268 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/src/main/scala/AxiStream.scala b/src/main/scala/AxiStream.scala new file mode 100644 index 0000000..1304078 --- /dev/null +++ b/src/main/scala/AxiStream.scala @@ -0,0 +1,12 @@ +package compaction_unit + +import chisel3._ +import chisel3.util._ + + +class AxiStreamIO(busWidth: Int) extends Bundle { + val tdata = Output(UInt(busWidth.W)) + val tvalid = Output(Bool()) + val tready = Input(Bool()) + val tlast = Output(Bool()) +} diff --git a/src/main/scala/DummyDecoder.scala b/src/main/scala/DummyDecoder.scala new file mode 100644 index 0000000..17bdbe2 --- /dev/null +++ b/src/main/scala/DummyDecoder.scala @@ -0,0 +1,84 @@ +package compaction_unit + +import chisel3._ +import chisel3.util._ + + +class DecoderInputIO(busWidth: Int) extends Bundle { + val axi_s = Flipped(new AxiStreamIO(busWidth)) +} + + +class DummyDecoder(busWidth: Int = 32) extends Module { + assert (busWidth == 32, "Currently only 32 bits bus is supported") + + val io = IO(new Bundle { + val input = new DecoderInputIO(busWidth) + val output = Flipped(new KvRingBufferInputIO(busWidth)) + + val readyToAccept = Input(Bool()) + val lastKvPairSeen = Output(Bool()) + }) + + // TODO: do not care about it for now but it might need a fix + io.input.axi_s.tlast <> DontCare + + val idle :: readKey :: readValue :: Nil = Enum(3) + val state = RegInit(idle) + val status = RegInit(0.U(busWidth.W)) + val lastSeen = RegInit(false.B) + + // 8-bit counter is enough to count up to 256 * 4 bytes (32-bits) = 1 KB + val counter = RegInit(0.U(8.W)) + + // First data from AXI is status + val keyLen = status(15, 8) - 1.U + val valueLen = status(23, 16) - 1.U + val isLastKvPair = status(0) + + switch (state) { + is (idle) { + when (io.input.axi_s.tvalid) { + state := readKey + status := io.input.axi_s.tdata + } + } + + is (readKey) { + when (io.input.axi_s.tvalid && io.input.axi_s.tready) { + counter := counter + 1.U + + when (counter === keyLen) { + state := readValue + counter := 0.U + } + } + } + + is (readValue) { + when (io.input.axi_s.tvalid && io.input.axi_s.tready) { + counter := counter + 1.U + + when (counter === valueLen) { + state := idle + counter := 0.U + lastSeen := isLastKvPair + } + } + } + } + + // TODO: readyToAccept maybe needs to be saved in register + io.input.axi_s.tready := io.readyToAccept + io.lastKvPairSeen := isLastKvPair + + io.output.enq.valid := (state === readKey || state === readValue) && io.input.axi_s.tvalid + io.output.enq.bits := io.input.axi_s.tdata + io.output.isInputKey := state === readKey + io.output.lastInput := state === readValue && counter === valueLen +} + +object Decoder extends App { + println("Generating the Decoder Verilog...") + (new chisel3.stage.ChiselStage).emitVerilog(new DummyDecoder(32), Array("--target-dir", "generated")) +} \ No newline at end of file diff --git a/src/main/scala/DummyEncoder.scala b/src/main/scala/DummyEncoder.scala new file mode 100644 index 0000000..3683c48 --- /dev/null +++ b/src/main/scala/DummyEncoder.scala @@ -0,0 +1,59 @@ +package compaction_unit + +import chisel3._ +import chisel3.util._ + + +class EncoderOutputIO(busWidth: Int) extends Bundle { + val axi_m = new AxiStreamIO(busWidth) +} + +class DummyEncoderIO(busWidth: Int) extends Bundle { + val input = Flipped(new KvRingBufferOutputIO(busWidth)) + val output = new EncoderOutputIO(busWidth) +} + + +class DummyEncoder(busWidth: Int = 32) extends Module { + assert (busWidth == 32, "Currently only 32 bits bus is supported") + + val io = IO(new DummyEncoderIO(busWidth)) + + val idle :: readValueLen :: outputStatus :: readKvPair :: Nil = Enum(4) + + val state = RegInit(idle) + val status = RegInit(0.U(busWidth.W)) + + switch (state) { + is (idle) { + when (io.input.metadataValid) { + status := Cat(status(31, 16), io.input.deq.bits(7, 0), status(7, 0)) + state := readValueLen + } + } + + is (readValueLen) { + when (io.input.metadataValid) { + status := Cat(status(31, 24), io.input.deq.bits(7, 0), status(15, 0)) + } + state := outputStatus + } + + is (outputStatus) { + when (io.output.axi_m.tready) { + state := readKvPair + } + } + + is (readKvPair) { + when (io.input.lastOutput && io.output.axi_m.tready) { + state := idle + } + } + } + io.input.outputKeyOnly := DontCare + io.input.deq.ready := state === readKvPair && io.output.axi_m.tready + io.output.axi_m.tdata := Mux(state === outputStatus, status, io.input.deq.bits) + io.output.axi_m.tvalid := state === outputStatus | io.input.deq.valid + io.output.axi_m.tlast := false.B +} diff --git a/src/main/scala/DummyKvPairFifo.scala b/src/main/scala/DummyKvPairFifo.scala new file mode 100644 index 0000000..73bc94e --- /dev/null +++ b/src/main/scala/DummyKvPairFifo.scala @@ -0,0 +1,44 @@ +package compaction_unit + +import chisel3._ +import chisel3.util._ +import chisel3.experimental.FlatIO + + +class DummyKvPairFifo(busWidth: Int = 32) extends Module { + assert (busWidth == 32, "Currently only 32 bits bus is supported") + + val io = IO(new Bundle { + val axi_s = Flipped(new AxiStreamIO(busWidth)) + val axi_m = new AxiStreamIO(busWidth) + }) + + val encoder = Module(new DummyEncoder(busWidth)) + val decoder = Module(new DummyDecoder(busWidth)) + val kvOutputBuffer = Module(new KVRingBuffer(4, busWidth, 4 * busWidth, 4 * busWidth, 2 * busWidth, autoReadNextPair = true)) + + kvOutputBuffer.io.full <> DontCare + kvOutputBuffer.io.empty <> DontCare + kvOutputBuffer.io.resetRead := false.B + kvOutputBuffer.io.moveReadPtr <> DontCare + + + encoder.io.input.deq <> kvOutputBuffer.io.deq + encoder.io.input.isOutputKey <> kvOutputBuffer.io.isOutputKey + encoder.io.input.lastOutput <> kvOutputBuffer.io.lastOutput + encoder.io.input.metadataValid <> kvOutputBuffer.io.metadataValid + encoder.io.input.outputKeyOnly <> kvOutputBuffer.io.outputKeyOnly + + encoder.io.output.axi_m <> io.axi_m + decoder.io.input.axi_s <> io.axi_s + + decoder.io.readyToAccept := true.B + decoder.io.output.enq <> kvOutputBuffer.io.enq + decoder.io.output.isInputKey <> kvOutputBuffer.io.isInputKey + decoder.io.output.lastInput <> kvOutputBuffer.io.lastInput +} + +object DummyKvPairFifoMain extends App { + println("Generating the dummy KV pair FIFO Verilog...") + (new chisel3.stage.ChiselStage).emitVerilog(new DummyKvPairFifo, Array("--target-dir", "Vivado/src/hdl", "--target:fpga")) +} diff --git a/src/main/scala/KvRingBuffer.scala b/src/main/scala/KvRingBuffer.scala index 9d0e1f9..c14fd45 100644 --- a/src/main/scala/KvRingBuffer.scala +++ b/src/main/scala/KvRingBuffer.scala @@ -3,21 +3,45 @@ package compaction_unit import chisel3._ import chisel3.util._ +// TODO: use this bundle in KvRingBuffer class +class KvRingBufferInputIO(busWidth: Int) extends Bundle { + val enq = Flipped(Decoupled(UInt(busWidth.W))) + val lastInput = Input(Bool()) + val isInputKey = Input(Bool()) +} + +// TODO: use this bundle in KvRingBuffer class +class KvRingBufferOutputIO(busWidth: Int) extends Bundle { + val deq = Decoupled(UInt(busWidth.W)) + val outputKeyOnly = Input(Bool()) + val lastOutput = Output(Bool()) + val isOutputKey = Output(Bool()) + + // hack to output key and value len + val metadataValid = Output(Bool()) +} + class KVRingBufferIO(busWidth: Int) extends Bundle { + // Input for KV pairs val enq = Flipped(Decoupled(UInt(busWidth.W))) - val deq = Decoupled(UInt(busWidth.W)) + val lastInput = Input(Bool()) // indicates the last input is presented to the buffer + val isInputKey = Input(Bool()) // is input value a key or a value + // Control inputs var moveReadPtr = Input(Bool()) // request buffer to stop reading and move read pointer to the next KV pair var resetRead = Input(Bool()) // request buffer to start reading current KV pair from the beginning + // Outputs + val deq = Decoupled(UInt(busWidth.W)) val outputKeyOnly = Input(Bool()) // indicates that only key should be outputted by the buffer - val lastInput = Input(Bool()) // indicates the last input is presented to the buffer - val isInputKey = Input(Bool()) // is input value a key or a value - val lastOutput = Output(Bool()) // indicates the last output is presented by the buffer val isOutputKey = Output(Bool()) // is output value a key or a value + // Outputs, hack to output key and value len + val metadataValid = Output(Bool()) + + // Status outputs val empty = Output(Bool()) val full = Output(Bool()) } @@ -33,7 +57,7 @@ class KVRingBufferIO(busWidth: Int) extends Bundle { * @param valueSize, the maximum size of the value in bits. * @param metadataSize, the maximum size of the metadata in bits. */ -class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: Int = 16, metadataSize: Int = 8) extends Module { +class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: Int = 16, metadataSize: Int = 8, autoReadNextPair: Boolean = false) extends Module { assert (depth > 1, "The KV buffer depth must be greater than 1") assert (busWidth > 0, "Bus width must be greater than 0") assert (keySize > 0, "Key size must be greater than 0") @@ -97,30 +121,42 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I val inputStateReg = RegInit(writeData) val outputStateReg = RegInit(requestKeyLen) + val writeReg = RegInit(0.U(busWidth.W)) + val offset = (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + val writeDataPtr = Mux(inputStateReg === writeData, Mux(io.isInputKey, metadataAddressOffset.U, (metadataAddressOffset + keyAddressOffset).U) + Mux(io.isInputKey, writeKeyChunkPtr, writeValueChunkPtr), 0.U) + val metadataOffsetPtr = Mux(inputStateReg === inputSaveValueLen, 1.U, 0.U) + + mem.write(writePtr * offset + writeDataPtr + metadataOffsetPtr, Mux(inputStateReg === writeData, io.enq.bits, writeReg)) + + //mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U, writeKeyChunkPtr) + //mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + 1.U, writeValueChunkPtr) + + switch(inputStateReg) { is(writeData) { when(io.enq.valid && !fullReg) { + //mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + (metadataAddressOffset + keyAddressOffset).U + writeValueChunkPtr, io.enq.bits) + when (io.isInputKey) { - mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + metadataAddressOffset.U + writeKeyChunkPtr, io.enq.bits) writeKeyChunkPtr := writeKeyChunkPtr + 1.U } otherwise { - mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + (metadataAddressOffset + keyAddressOffset).U + writeValueChunkPtr, io.enq.bits) writeValueChunkPtr := writeValueChunkPtr + 1.U - when(io.lastInput) { inputStateReg := inputSaveKeyLen + writeReg := writeKeyChunkPtr } } } } is(inputSaveKeyLen) { - mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U, writeKeyChunkPtr) + //mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U, writeKeyChunkPtr) inputStateReg := inputSaveValueLen + writeReg := writeValueChunkPtr } is(inputSaveValueLen) { - mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + 1.U, writeValueChunkPtr) + //mem.write(writePtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + 1.U, writeValueChunkPtr) emptyReg := false.B incrWrite := true.B fullReg := nextWrite === readPtr @@ -140,7 +176,7 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I } } - val readFullPtr = readPtr * (metadataAddressOffset + keyAddressOffset + valueAddressOffset).U + readValueChunkPtr + readKeyChunkPtr + val readFullPtr = readPtr * offset + readValueChunkPtr + readKeyChunkPtr val data = mem.read(readFullPtr) val shadowReg = RegInit(0.U(busWidth.W)) @@ -244,7 +280,7 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I is(waitForReadLastKeyChunk) { when(io.deq.ready && !moveOrResetRequested) { when(io.outputKeyOnly) { - outputStateReg := requestKeyLen + outputStateReg := requestKeyLen } otherwise { when(valueLen === 1.U) { outputStateReg := readLastValueChunk @@ -261,6 +297,9 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I when(io.deq.ready) { when(readValueChunkPtr === valueLen - 1.U) { outputStateReg := readLastValueChunk + // TODO: need to investigate why this is needed here, + // some tests fail if you comment it out, + // it should be enough to set emptyReg in readLast* states emptyReg := nextRead === writePtr } otherwise { readValueChunkPtr := readValueChunkPtr + 1.U @@ -277,8 +316,12 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I when(io.deq.ready && !moveOrResetRequested) { when(readValueChunkPtr === valueLen - 1.U) { outputStateReg := readLastValueChunk + // TODO: need to investigate why this is needed here, + // some tests fail if you comment it out, + // it should be enough to set emptyReg in readLast* states emptyReg := nextRead === writePtr } otherwise { + outputStateReg := outputReadValue readValueChunkPtr := readValueChunkPtr + 1.U } } @@ -288,6 +331,10 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I when (!moveOrResetRequested) { when(io.deq.ready) { outputStateReg := requestKeyLen + emptyReg := nextRead === writePtr + if (autoReadNextPair) { + incrRead := true.B + } } .otherwise { shadowReg := data @@ -299,6 +346,11 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I is(waitForReadLastValueChunk) { when(io.deq.ready && !moveOrResetRequested) { outputStateReg := requestKeyLen + emptyReg := nextRead === writePtr + + if (autoReadNextPair) { + incrRead := true.B + } } } } @@ -310,6 +362,8 @@ class KVRingBuffer(depth: Int, busWidth: Int = 4, keySize: Int = 8, valueSize: I io.lastOutput := (outputStateReg === readLastValueChunk || outputStateReg === waitForReadLastValueChunk) || ((outputStateReg === readLastKeyChunk || outputStateReg === waitForReadLastKeyChunk) && io.outputKeyOnly) io.empty := emptyReg io.full := fullReg + + io.metadataValid := outputStateReg === outputReadKeyLen || outputStateReg === outputReadValueLen } object KvRingBufferMain extends App { diff --git a/src/main/scala/KvTransfer.scala b/src/main/scala/KvTransfer.scala index 63e5c6c..fdcf356 100644 --- a/src/main/scala/KvTransfer.scala +++ b/src/main/scala/KvTransfer.scala @@ -22,12 +22,14 @@ class KvTransferIO(busWidth: Int, numberOfBuffers: Int = 4) extends Bundle { // inputs and outputs for control of the module val command = Input(UInt(2.W)) val stop = Input(Bool()) + // TODO: bufferInputSelect can be replaced with mask val bufferInputSelect = Input(UInt(log2Ceil(numberOfBuffers).W)) + val mask = Input(UInt(numberOfBuffers.W)) val busy = Output(Bool()) // outputs for key buffer and KV output buffer val deq = Decoupled(UInt(busWidth.W)) - val incrKeyBufferPtr = Output(Bool()) + val incrKeyBufferPtr = Output(Bool()) // only valid if deq.valid is True val clearKeyBuffer = Output(Bool()) val isOutputKey = Output(Bool()) val lastOutput = Output(Bool()) // outputs whatever current key chunk is the last one, only valid if deq.valid is True @@ -37,12 +39,12 @@ class KvTransferIO(busWidth: Int, numberOfBuffers: Int = 4) extends Bundle { /** A class for KV transfer module. * This module is used to transfer KV pairs to Comparator module when requested. * The module supports following commands: - * 00: + * Command 0 (b00): * Does nothing, waits for the command. - * 01: + * Command 1 (b01): * Transfers key chunks from all buffers, one-by-one, until all buffers are empty. - * 10: - * Transfers selected KV pair from KV Ring Buffer to KV Output buffer. + * Command 2 (b10): + * Transfers KV pair from selected KV Ring Buffer to KV Output buffer. * * @param busWidth, the number of bits that can be read from memory at once. * @param numberOfBuffers, the number of buffers that will be connected to the KV transfer module. @@ -58,22 +60,35 @@ class KvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module { val state = RegInit(idle) val data = RegInit(0.U(busWidth.W)) val lastKeyChunk = RegInit(false.B) + val mask = RegInit(0.U(numberOfBuffers.W)) - // Used by command 1 (b01) and 2 (b10) + // Used by command 1 and 2 val bufferIdx = RegInit(0.U(log2Ceil(numberOfBuffers).W)) - // Used by command 1 (b01) + // Used by command 1 val moreChunksToLoad = RegInit(VecInit(Seq.fill(numberOfBuffers)(true.B))) val allBuffersEmpty = Cat(moreChunksToLoad) === 0.U + val nextIndexSelector = Module(new NextIndexSelector(numberOfBuffers)) + nextIndexSelector.io.mask := moreChunksToLoad.asUInt + nextIndexSelector.io.currentIndex := bufferIdx + switch (state) { is (idle) { - // Reset variables - moreChunksToLoad.foreach(_ := true.B) - + // Start command to trasnfer keys to Key Buffer when (io.command === "b01".U) { - bufferIdx := 0.U + bufferIdx := PriorityEncoder(io.mask) state := clearKeyBuffer + mask := io.mask + + // Reset moreChunksToLoad + for (i <- 0 until numberOfBuffers) { + when (io.mask(i) === 0.U) { + moreChunksToLoad(i) := false.B + } .otherwise { + moreChunksToLoad(i) := true.B + } + } } when (io.command === "b10".U) { @@ -88,7 +103,7 @@ class KvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module { when (io.stop === false.B && moreChunksToLoad(bufferIdx) === true.B) { when (io.enq.valid) { when (io.deq.ready) { - bufferIdx := bufferIdx + 1.U + bufferIdx := nextIndexSelector.io.nextIndex } .otherwise { // Data is not transferred this clock cycle, store and wait until it will be received. data := io.enq.bits @@ -102,7 +117,7 @@ class KvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module { state := idle } .otherwise { // Only this buffer is empty, move to the next one. - bufferIdx := bufferIdx + 1.U + bufferIdx := nextIndexSelector.io.nextIndex } } @@ -117,7 +132,7 @@ class KvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module { } is (waitForTransfer) { when (io.deq.ready && !io.stop) { - bufferIdx := bufferIdx + 1.U + bufferIdx := nextIndexSelector.io.nextIndex state := loadChunk } @@ -154,10 +169,7 @@ class KvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module { // input buffers need to be reset when we start loading new chunks, or transfer KV pair io.resetBufferRead := state === resetBufferRead || state === clearKeyBuffer - // this works when we iterate over all buffers, - // but it will not work if we want to load only non-empty buffers - // because buffer with index 3 might be skipped. - io.incrKeyBufferPtr := bufferIdx === (numberOfBuffers-1).U && (state === loadChunk || state === waitForTransfer) + io.incrKeyBufferPtr := nextIndexSelector.io.overflow && (state === loadChunk || state === waitForTransfer) io.enq.ready := (state === loadChunk && moreChunksToLoad(bufferIdx) === true.B) || (state === transferKvPair && io.deq.ready) io.deq.bits := Mux(state === waitForTransfer, data, io.enq.bits) @@ -182,6 +194,7 @@ class TopKvTransferIO(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Bundl val stop = Input(Bool()) val bufferInputSelect = Input(UInt(log2Ceil(numberOfBuffers).W)) val busy = Output(Bool()) + val mask = Input(UInt(numberOfBuffers.W)) // TODO: outputs are copied from KvTransfer module, not good to have duplicate code val bufferSelect = Output(UInt(log2Ceil(numberOfBuffers).W)) @@ -204,15 +217,16 @@ class TopKvTransfer(busWidth: Int = 4, numberOfBuffers: Int = 4) extends Module val kvTransfer = Module(new KvTransfer(busWidth, numberOfBuffers)) - // kvTransfer inputs + // kvTransfer controls kvTransfer.io.bufferInputSelect <> io.bufferInputSelect kvTransfer.io.command <> io.command kvTransfer.io.stop <> io.stop + kvTransfer.io.busy <> io.busy + kvTransfer.io.mask <> io.mask // kvTransfer outputs kvTransfer.io.deq <> DontCare kvTransfer.io.bufferSelect <> io.bufferSelect - kvTransfer.io.busy <> io.busy kvTransfer.io.incrKeyBufferPtr <> io.incrKeyBufferPtr kvTransfer.io.clearKeyBuffer <> io.clearKeyBuffer diff --git a/src/main/scala/Merger.scala b/src/main/scala/Merger.scala index f23df0b..fc687f4 100644 --- a/src/main/scala/Merger.scala +++ b/src/main/scala/Merger.scala @@ -5,18 +5,19 @@ import chisel3.util._ class MergerIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { + // Inputs from KeyBuffer module val enq = Flipped(Decoupled(UInt(busWidth.W))) - val bufferInputSelect = Input(UInt(log2Ceil(numberOfBuffers).W)) val lastInput = Input(Bool()) + // Control inputs from Controller module val reset = Input(Bool()) + val mask = Input(UInt(numberOfBuffers.W)) + // Output for Controller module val isResultValid = Output(Bool()) - val haveWinner = Output(Bool()) val winnerIndex = Output(UInt(log2Ceil(numberOfBuffers).W)) - val nextKvPairsToLoad = Output(Vec(numberOfBuffers, Bool())) } @@ -42,6 +43,9 @@ class MergerIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { * Important: after the winner is found, the module will not allow any changes to the inputs. * It will keep returning the winning results and wait for reset signal. * The outside module is responsible for resetting the Merger module. + * + * Important: when io.reset is set to true, io.mask needs to be set by control module as well. + * This new mask will be used as a starting one for the comparison. * * @param busWidth, the number of bits . * @param numberOfBuffers, how many buffers will be compared. @@ -101,7 +105,7 @@ class Merger(busWidth: Int, numberOfBuffers: Int) extends Module { is(haveWinner) { when (io.reset) { - mask := ((1 << numberOfBuffers) - 1).U(numberOfBuffers.W) + mask := io.mask state := comparingKeyChunks } } diff --git a/src/main/scala/NextIndexSelector.scala b/src/main/scala/NextIndexSelector.scala new file mode 100644 index 0000000..4a6dd2a --- /dev/null +++ b/src/main/scala/NextIndexSelector.scala @@ -0,0 +1,40 @@ +package compaction_unit + +import chisel3._ +import chisel3.util._ + + +/** A class for combinational NextIndexSelector + * This module is used to select next index based on current index and mask. + * More examples of how this module works can be found in the tests. + * + * @param n, number of indexes. + */ +class NextIndexSelector(n: Int) extends Module { + val io = IO(new Bundle { + val mask = Input(UInt(n.W)) + val currentIndex = Input(UInt(log2Ceil(n).W)) + + val nextIndex = Output(UInt(log2Ceil(n).W)) + val overflow = Output(Bool()) + }) + + // Disable all indexes that are less than currentIndex + val modifiedMask = Wire(Vec(n, Bool())) + for (i <- 0 until n) { + when (i.U <= io.currentIndex) { + modifiedMask(i) := false.B + }.otherwise { + modifiedMask(i) := io.mask(i) + } + } + + // We do not have any indexes on the left side of currentIndex, use original mask + when (Cat(modifiedMask).asUInt === 0.U) { + io.nextIndex := PriorityEncoder(io.mask) + io.overflow := true.B + }.otherwise { + io.nextIndex := PriorityEncoder(modifiedMask.asUInt) + io.overflow := false.B + } +} diff --git a/src/test/scala/DummyDecoderSpec.scala b/src/test/scala/DummyDecoderSpec.scala new file mode 100644 index 0000000..80b84d0 --- /dev/null +++ b/src/test/scala/DummyDecoderSpec.scala @@ -0,0 +1,55 @@ +package compaction_unit + +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec +import chisel3.experimental.BundleLiterals._ + + +class DummyDecoderSpec extends AnyFreeSpec with ChiselScalatestTester { + val statusIsLast2Keys4Values = 0x00040201 + val statusNotLast2Keys4Values = 0x00040200 + + "Transfer last KV Pair from AXI to buffer" in { + test(new DummyDecoder).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + dut.io.readyToAccept.poke(true.B) + dut.io.input.axi_s.tvalid.poke(true.B) + + dut.io.input.axi_s.tready.expect(true.B) + + // Send status data + dut.io.input.axi_s.tdata.poke(statusIsLast2Keys4Values.U) + dut.io.lastKvPairSeen.expect(false.B) + dut.io.output.enq.valid.expect(false.B) + dut.clock.step() + + // Send key + for (i <- 0 until 2) { + dut.io.input.axi_s.tready.expect(true.B) + dut.io.input.axi_s.tdata.poke((i + 1000).U) + dut.io.output.enq.valid.expect(true.B) + dut.io.output.enq.bits.expect((i + 1000).U) + dut.io.output.isInputKey.expect(true.B) + dut.io.output.lastInput.expect(false.B) + dut.clock.step() + } + + // Send value + for (i <- 0 until 4) { + dut.io.input.axi_s.tready.expect(true.B) + dut.io.input.axi_s.tdata.poke((i + 2000).U) + dut.io.output.enq.valid.expect(true.B) + dut.io.output.enq.bits.expect((i + 2000).U) + dut.io.output.isInputKey.expect(false.B) + if (i == 3) { + dut.io.output.lastInput.expect(true.B) + } else { + dut.io.output.lastInput.expect(false.B) + } + dut.clock.step() + } + dut.io.output.enq.valid.expect(false.B) + dut.io.lastKvPairSeen.expect(true.B) + } + } +} diff --git a/src/test/scala/DummyEncoderSpec.scala b/src/test/scala/DummyEncoderSpec.scala new file mode 100644 index 0000000..5a91610 --- /dev/null +++ b/src/test/scala/DummyEncoderSpec.scala @@ -0,0 +1,74 @@ +package compaction_unit + +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec +import chisel3.experimental.BundleLiterals._ + + +class DummyEncoderSpec extends AnyFreeSpec with ChiselScalatestTester { + val statusNotLast2Keys4Values = 0x00040200 + + "Transfer KV Pair from output buffer to AXI Stream interface" in { + test(new DummyEncoder).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + // Default setup + dut.io.input.deq.ready.expect(false.B) + dut.io.output.axi_m.tvalid.expect(false.B) + dut.io.output.axi_m.tlast.expect(false.B) + + dut.io.output.axi_m.tready.poke(true.B) + dut.io.input.deq.valid.poke(false.B) + + // Send key length + dut.io.input.metadataValid.poke(true.B) + dut.io.input.deq.bits.poke(2.U) + dut.clock.step() + + // Send value length + dut.io.output.axi_m.tvalid.expect(false.B) + dut.io.input.deq.ready.expect(false.B) + dut.io.input.deq.bits.poke(4.U) + dut.clock.step() + dut.io.input.metadataValid.poke(false.B) + + // At this point KV buffer will output valid results but we do not read yet + dut.io.input.deq.valid.poke(true.B) + + // Read status + dut.io.input.deq.ready.expect(false.B) + dut.io.output.axi_m.tvalid.expect(true.B) + dut.io.output.axi_m.tdata.expect(statusNotLast2Keys4Values.U) + dut.clock.step() + + // Send some data + for (i <- 0 until 3) { + dut.io.input.deq.ready.expect(true.B) + dut.io.input.deq.bits.poke((i + 1000).U) + dut.io.output.axi_m.tvalid.expect(true.B) + dut.io.output.axi_m.tdata.expect((i + 1000).U) + dut.clock.step() + } + + // Send rest of the data + for (i <- 3 until 6) { + // AXI not ready for one clock + dut.io.output.axi_m.tready.poke(false.B) + dut.io.input.deq.ready.expect(false.B) + dut.clock.step() + dut.io.output.axi_m.tready.poke(true.B) + + dut.io.input.deq.ready.expect(true.B) + dut.io.input.deq.bits.poke((i + 1000).U) + if (i == 5) { + dut.io.input.lastOutput.poke(true.B) + } + dut.io.output.axi_m.tvalid.expect(true.B) + dut.io.output.axi_m.tdata.expect((i + 1000).U) + dut.clock.step() + } + dut.io.input.deq.valid.poke(false.B) + dut.io.input.deq.ready.expect(false.B) + dut.io.output.axi_m.tvalid.expect(false.B) + } + } +} diff --git a/src/test/scala/DummyKvPairFifoSpec.scala b/src/test/scala/DummyKvPairFifoSpec.scala new file mode 100644 index 0000000..6b48aa9 --- /dev/null +++ b/src/test/scala/DummyKvPairFifoSpec.scala @@ -0,0 +1,77 @@ +package compaction_unit + +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec +import chisel3.experimental.BundleLiterals._ + + +class DummyKvPairFifoSpec extends AnyFreeSpec with ChiselScalatestTester { + val statusNotLast2Keys4Values = 0x00040200 + + "AXI S to KV output buffer to AXI M" in { + test(new DummyKvPairFifo).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + // Send status data + dut.io.axi_s.tdata.poke(statusNotLast2Keys4Values.U) + dut.io.axi_s.tready.expect(true.B) + dut.io.axi_s.tvalid.poke(true.B) + dut.clock.step() + + // Send key + for (i <- 0 until 2) { + dut.io.axi_s.tready.expect(true.B) + dut.io.axi_s.tdata.poke((i + 1000).U) + dut.clock.step() + } + + // Send value + for (i <- 0 until 4) { + dut.io.axi_s.tready.expect(true.B) + dut.io.axi_s.tdata.poke((i + 2000).U) + if (i == 3) { + dut.io.axi_s.tlast.poke(true.B) + } + dut.clock.step() + } + dut.io.axi_s.tvalid.poke(false.B) + dut.io.axi_s.tlast.poke(false.B) + + // Wait for AXI M to be ready + dut.io.axi_m.tready.poke(true.B) + while (dut.io.axi_m.tvalid.peek().litToBoolean == false) { + dut.clock.step() + } + + // Read status + dut.io.axi_m.tdata.expect(statusNotLast2Keys4Values.U) + dut.clock.step() + + // Read key + for (i <- 0 until 2) { + dut.io.axi_m.tvalid.expect(true.B) + dut.io.axi_m.tdata.expect((i + 1000).U) + dut.clock.step() + } + + // One clock cycle output is not ready + dut.io.axi_m.tready.poke(false.B) + dut.clock.step() + dut.io.axi_m.tready.poke(true.B) + + // Read value + for (i <- 0 until 4) { + dut.io.axi_m.tvalid.expect(true.B) + dut.io.axi_m.tdata.expect((i + 2000).U) + dut.clock.step() + } + dut.io.axi_m.tvalid.expect(false.B) + dut.io.axi_m.tlast.expect(false.B) + + // imagine output still wants to read + dut.io.axi_m.tready.poke(true.B) + dut.clock.step() + dut.io.axi_m.tvalid.expect(false.B) + dut.io.axi_m.tlast.expect(false.B) + } + } +} diff --git a/src/test/scala/KvRingBufferSpec.scala b/src/test/scala/KvRingBufferSpec.scala index 230d793..36d416c 100644 --- a/src/test/scala/KvRingBufferSpec.scala +++ b/src/test/scala/KvRingBufferSpec.scala @@ -94,18 +94,28 @@ class KvRingBufferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.lastInput.poke(true.B) dut.clock.step() - // Wait for KV data to be written to memory dut.io.enq.valid.poke(false.B) dut.io.lastInput.poke(false.B) dut.io.enq.ready.expect(false.B) - dut.clock.step(2) + + // wait for metadata to be ready + while (dut.io.metadataValid.peek().litToBoolean == false) { + dut.clock.step() + } + dut.io.empty.expect(false.B) - dut.io.enq.ready.expect(true.B) - // delay to read metadata - dut.clock.step(2) - - dut.io.enq.ready.expect(true.B) + // read key len + dut.io.deq.bits.expect(2.U) + dut.io.deq.valid.expect(false.B) + dut.io.metadataValid.expect(true.B) + dut.clock.step() + + // read value len + dut.io.deq.bits.expect(3.U) + dut.io.deq.valid.expect(false.B) + dut.io.metadataValid.expect(true.B) + dut.clock.step() // Start reading KV pair dut.io.deq.ready.poke(true.B) @@ -265,6 +275,77 @@ class KvRingBufferSpec extends AnyFreeSpec with ChiselScalatestTester { } } + "Should write two KV pairs and read two back" in { + test(new KVRingBuffer(4, busWidth = 4, keySize = 12, valueSize = 12, metadataSize = 8, autoReadNextPair = true)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + setDefaultValues(dut) + dut.clock.step() + + // Write KV pair 1 + dut.io.enq.ready.expect(true.B) + dut.io.enq.bits.poke(0xA.U) + dut.io.enq.valid.poke(true.B) + dut.io.isInputKey.poke(true.B) + dut.clock.step() + + dut.io.isInputKey.poke(false.B) + dut.io.lastInput.poke(true.B) + dut.io.enq.bits.poke(0xC.U) + dut.clock.step() + dut.io.enq.valid.poke(false.B) + + while (dut.io.enq.ready.peek().litToBoolean == false) { + dut.clock.step() + } + + // Write KV pair 2 + dut.io.enq.bits.poke(0xB.U) + dut.io.enq.valid.poke(true.B) + dut.io.isInputKey.poke(true.B) + dut.clock.step() + + dut.io.isInputKey.poke(false.B) + dut.io.lastInput.poke(true.B) + dut.io.enq.bits.poke(0xD.U) + dut.clock.step() + dut.io.enq.valid.poke(false.B) + + // Start reading KV pairs + dut.io.deq.ready.poke(true.B) + + while (dut.io.deq.valid.peek().litToBoolean == false) { + dut.clock.step() + } + + // Read first KV pair + dut.io.deq.bits.expect(0xA.U) + dut.io.isOutputKey.expect(true.B) + dut.clock.step() + + dut.io.deq.bits.expect(0xC.U) + dut.io.isOutputKey.expect(false.B) + dut.io.lastOutput.expect(true.B) + dut.clock.step() + + while (dut.io.deq.valid.peek().litToBoolean == false) { + dut.clock.step() + } + + // Read second KV pair + dut.io.deq.bits.expect(0xB.U) + dut.io.isOutputKey.expect(true.B) + dut.clock.step() + + dut.io.deq.bits.expect(0xD.U) + dut.io.isOutputKey.expect(false.B) + dut.io.lastOutput.expect(true.B) + dut.clock.step() + + dut.io.deq.valid.expect(false.B) + dut.io.empty.expect(true.B) + dut.io.full.expect(false.B) + } + } + "Should move to read the next KV pair" in { test(new KVRingBuffer(4, busWidth = 4, keySize = 12, valueSize = 12, metadataSize = 8)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => setDefaultValues(dut) @@ -411,11 +492,14 @@ class KvRingBufferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.enq.bits.poke(0xC.U) dut.clock.step() - dut.io.isInputKey.poke(false.B) - dut.io.lastInput.poke(true.B) dut.io.enq.bits.poke(0xD.U) dut.clock.step() + dut.io.lastInput.poke(true.B) + dut.io.enq.bits.poke(0xE.U) + dut.clock.step() + + dut.io.lastInput.poke(false.B) dut.io.enq.valid.poke(false.B) // Reading KV pair with delay @@ -474,19 +558,40 @@ class KvRingBufferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.deq.ready.poke(false.B) dut.io.deq.bits.expect(0xD.U) dut.io.isOutputKey.expect(false.B) - dut.io.lastOutput.expect(true.B) + dut.io.lastOutput.expect(false.B) dut.io.deq.valid.expect(true.B) dut.clock.step() dut.io.deq.bits.expect(0xD.U) dut.io.isOutputKey.expect(false.B) - dut.io.lastOutput.expect(true.B) + dut.io.lastOutput.expect(false.B) dut.io.deq.valid.expect(true.B) dut.clock.step() dut.io.deq.ready.poke(true.B) dut.io.deq.bits.expect(0xD.U) dut.io.isOutputKey.expect(false.B) + dut.io.lastOutput.expect(false.B) + dut.io.deq.valid.expect(true.B) + dut.clock.step() + + // Check if third value chunk is kept until 'ready' asserted + dut.io.deq.ready.poke(false.B) + dut.io.deq.bits.expect(0xE.U) + dut.io.isOutputKey.expect(false.B) + dut.io.lastOutput.expect(true.B) + dut.io.deq.valid.expect(true.B) + dut.clock.step() + + dut.io.deq.bits.expect(0xE.U) + dut.io.isOutputKey.expect(false.B) + dut.io.lastOutput.expect(true.B) + dut.io.deq.valid.expect(true.B) + dut.clock.step() + + dut.io.deq.ready.poke(true.B) + dut.io.deq.bits.expect(0xE.U) + dut.io.isOutputKey.expect(false.B) dut.io.lastOutput.expect(true.B) dut.io.deq.valid.expect(true.B) dut.clock.step() diff --git a/src/test/scala/KvRingBuffersAndKvTransferAndKeyBufferSpec.scala b/src/test/scala/KvRingBuffersAndKvTransferAndKeyBufferSpec.scala index af6cb35..d6dfe3b 100644 --- a/src/test/scala/KvRingBuffersAndKvTransferAndKeyBufferSpec.scala +++ b/src/test/scala/KvRingBuffersAndKvTransferAndKeyBufferSpec.scala @@ -28,6 +28,7 @@ class TestKvTransferIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { val command = Input(UInt(2.W)) val stop = Input(Bool()) val busy = Output(Bool()) + val mask = Input(UInt(numberOfBuffers.W)) } class TestKeyBufferIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { @@ -40,6 +41,7 @@ class TestKeyBufferIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { class TestMergerIO(busWidth: Int, numberOfBuffers: Int) extends Bundle { val reset = Input(Bool()) + val mask = Input(UInt(numberOfBuffers.W)) val isResultValid = Output(Bool()) val haveWinner = Output(Bool()) @@ -96,6 +98,7 @@ class TopTestModule(busWidth: Int, numberOfBuffers: Int) extends Module { topKvTransfer.io.stop <> io.kvTransfer.stop topKvTransfer.io.command <> io.kvTransfer.command topKvTransfer.io.busy <> io.kvTransfer.busy + topKvTransfer.io.mask <> io.kvTransfer.mask topKvTransfer.io.deqKvPair <> DontCare // connect TopKvTransfer to KeyBuffer @@ -154,6 +157,7 @@ class TopTestMergerModule(busWidth: Int, numberOfBuffers: Int) extends Module { topKvTransfer.io.stop <> io.kvTransfer.stop topKvTransfer.io.command <> io.kvTransfer.command topKvTransfer.io.busy <> io.kvTransfer.busy + topKvTransfer.io.mask <> io.kvTransfer.mask // connect TopKvTransfer to KeyBuffer keyBuffer.io.enq <> topKvTransfer.io.deq @@ -173,6 +177,7 @@ class TopTestMergerModule(busWidth: Int, numberOfBuffers: Int) extends Module { io.merger.winnerIndex <> merger.io.winnerIndex io.merger.nextKvPairsToLoad <> merger.io.nextKvPairsToLoad io.merger.reset <> merger.io.reset + io.merger.mask <> merger.io.mask // Connect output of KvTransfer to input of KVOutputBuffer kvOutputBuffer.io.enq <> topKvTransfer.io.deqKvPair @@ -257,6 +262,7 @@ class KvRingBuffersAndKvTransferAndKeyBufferSpec extends AnyFreeSpec with Chisel // Send command to KvTransfer to start filling KeyBuffer with chunks dut.io.kvTransfer.command.poke("b01".U) + dut.io.kvTransfer.mask.poke("b1111".U) dut.clock.step() dut.io.kvTransfer.command.poke("b00".U) @@ -348,6 +354,7 @@ class KvRingBuffersAndKvTransferAndKeyBufferSpec extends AnyFreeSpec with Chisel dut.io.buffers(i).isInputKey.poke(false.B) } dut.io.merger.reset.poke(true.B) + dut.io.merger.mask.poke("b1111".U) dut.clock.step() dut.io.merger.reset.poke(false.B) @@ -428,6 +435,7 @@ class KvRingBuffersAndKvTransferAndKeyBufferSpec extends AnyFreeSpec with Chisel // Send command to KvTransfer to start filling KeyBuffer with chunks dut.io.kvTransfer.command.poke("b01".U) + dut.io.kvTransfer.mask.poke("b1111".U) dut.clock.step() dut.io.kvTransfer.command.poke("b00".U) diff --git a/src/test/scala/KvTransferSpec.scala b/src/test/scala/KvTransferSpec.scala index fe8b670..293e82d 100644 --- a/src/test/scala/KvTransferSpec.scala +++ b/src/test/scala/KvTransferSpec.scala @@ -9,13 +9,14 @@ import chisel3.experimental.BundleLiterals._ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { "Should stop loading key chunks when requested" in { - test(new KvTransfer(4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + test(new KvTransfer(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // set inputs to default dut.io.enq.bits.poke(0.U) dut.io.lastInput.poke(false.B) dut.io.enq.valid.poke(false.B) dut.io.deq.ready.poke(false.B) dut.io.stop.poke(false.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.enq.ready.expect(false.B) @@ -133,7 +134,7 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { } "Should load a single key chunk with delayed ready" in { - test(new KvTransfer(4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + test(new KvTransfer(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // set inputs to default dut.io.enq.bits.poke(0.U) dut.io.lastInput.poke(false.B) @@ -141,6 +142,7 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.deq.ready.poke(false.B) dut.io.stop.poke(false.B) dut.io.clearKeyBuffer.expect(false.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.enq.ready.expect(false.B) @@ -210,6 +212,7 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.clearKeyBuffer.expect(false.B) dut.clock.step() + dut.io.enq.valid.poke(false.B) } dut.io.lastInput.poke(true.B) @@ -271,12 +274,12 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.clearKeyBuffer.expect(false.B) dut.clock.step() + dut.io.enq.valid.poke(false.B) } // all buffers are empty, command is finished dut.io.busy.expect(true.B) dut.io.enq.ready.expect(false.B) - dut.io.bufferSelect.expect(0.U) dut.io.deq.valid.expect(false.B) dut.io.clearKeyBuffer.expect(false.B) @@ -286,17 +289,17 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.clearKeyBuffer.expect(false.B) dut.io.deq.valid.expect(false.B) dut.io.enq.ready.expect(false.B) - dut.io.bufferSelect.expect(0.U) } } "Should load a single key chunk with on-time ready" in { - test(new KvTransfer(4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + test(new KvTransfer(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => dut.io.enq.bits.poke(0.U) dut.io.lastInput.poke(false.B) dut.io.enq.valid.poke(false.B) dut.io.deq.ready.poke(false.B) dut.io.stop.poke(false.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.enq.ready.expect(false.B) @@ -383,34 +386,85 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { // remaining buffers have last input set to true dut.io.lastInput.poke(true.B) - // buffers that are already empty should be skipped - for (i <- 0 until 2) { + for (i <- 2 until 4) { + dut.io.enq.valid.poke(true.B) + dut.io.enq.bits.poke((0xA + i).U) dut.io.deq.ready.poke(true.B) - dut.io.enq.ready.expect(false.B) + dut.io.enq.ready.expect(true.B) dut.io.busy.expect(true.B) dut.io.bufferSelect.expect(i.U) - dut.io.deq.valid.expect(false.B) - dut.io.incrKeyBufferPtr.expect(false.B) + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.expect((0xA + i).U) + dut.io.lastOutput.expect(true.B) + + // on last buffer, we should increment key buffer pointer + if (i == 3) { + dut.io.incrKeyBufferPtr.expect(true.B) + } else { + dut.io.incrKeyBufferPtr.expect(false.B) + } dut.io.clearKeyBuffer.expect(false.B) dut.clock.step() } - for (i <- 2 until 4) { + // all buffers are empty, command is finished + dut.io.busy.expect(true.B) + dut.io.enq.ready.expect(false.B) + dut.io.deq.valid.expect(false.B) + dut.io.clearKeyBuffer.expect(false.B) + + dut.clock.step() + + dut.io.busy.expect(false.B) + dut.io.clearKeyBuffer.expect(false.B) + dut.io.deq.valid.expect(false.B) + dut.io.enq.ready.expect(false.B) + } + } + + "Should transfer key chunks from selected buffers to deq" in { + test(new KvTransfer(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + dut.io.enq.bits.poke(0.U) + dut.io.lastInput.poke(false.B) + dut.io.enq.valid.poke(false.B) + dut.io.deq.ready.poke(false.B) + dut.io.stop.poke(false.B) + + // Select only buffers 1 and 2 + dut.io.mask.poke("b0110".U) + dut.clock.step() + + // send transfer command + dut.io.command.poke("b01".U) + dut.io.enq.ready.expect(false.B) + dut.io.deq.valid.expect(false.B) + dut.io.busy.expect(false.B) + dut.io.incrKeyBufferPtr.expect(false.B) + dut.clock.step() + + // reset command to "neutral" + dut.io.command.poke("b00".U) + dut.io.clearKeyBuffer.expect(true.B) + dut.io.deq.valid.expect(false.B) + dut.clock.step() + + // Load first chunks from selected buffers + for (i <- List(1, 2)) { dut.io.enq.valid.poke(true.B) - dut.io.enq.bits.poke((0xA + i).U) + dut.io.enq.bits.poke((0x1 + i).U) dut.io.deq.ready.poke(true.B) dut.io.enq.ready.expect(true.B) dut.io.busy.expect(true.B) dut.io.bufferSelect.expect(i.U) dut.io.deq.valid.expect(true.B) - dut.io.deq.bits.expect((0xA + i).U) - dut.io.lastOutput.expect(true.B) + dut.io.lastOutput.expect(false.B) + dut.io.deq.bits.expect((0x1 + i).U) // on last buffer, we should increment key buffer pointer - if (i == 3) { + if (i == 2) { dut.io.incrKeyBufferPtr.expect(true.B) } else { dut.io.incrKeyBufferPtr.expect(false.B) @@ -419,25 +473,70 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.clock.step() } + + // Buffer 1 will have last key chunk + // Buffer 2 still has some chunks left + for (i <- List(1, 2)) { + if (i == 1) { + dut.io.lastInput.poke(true.B) + } else { + dut.io.lastInput.poke(false.B) + } + dut.io.enq.valid.poke(true.B) + dut.io.enq.bits.poke((0x6 + i).U) + dut.io.deq.ready.poke(true.B) - // all buffers are empty, command is finished + dut.io.enq.ready.expect(true.B) + dut.io.busy.expect(true.B) + dut.io.bufferSelect.expect(i.U) + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.expect((0x6 + i).U) + + if (i == 1) { + dut.io.lastOutput.expect(true.B) + } else { + dut.io.lastOutput.expect(false.B) + } + dut.io.clearKeyBuffer.expect(false.B) + + dut.clock.step() + } + + // Last key chunk for buffer 2 + dut.io.lastInput.poke(true.B) + dut.io.enq.valid.poke(true.B) + dut.io.enq.bits.poke(0xE.U) + dut.io.deq.ready.poke(true.B) + + dut.io.enq.ready.expect(true.B) + dut.io.busy.expect(true.B) + dut.io.bufferSelect.expect(2.U) + dut.io.deq.valid.expect(true.B) + dut.io.deq.bits.expect(0xE.U) + dut.io.lastOutput.expect(true.B) + dut.io.clearKeyBuffer.expect(false.B) + + dut.clock.step() + dut.io.lastInput.poke(false.B) + dut.io.enq.valid.poke(false.B) + + // All buffers are empty, need one cycle to check and finish command dut.io.busy.expect(true.B) dut.io.enq.ready.expect(false.B) - dut.io.bufferSelect.expect(0.U) dut.io.deq.valid.expect(false.B) dut.io.clearKeyBuffer.expect(false.B) dut.clock.step() - + + // Ready to accept new commands dut.io.busy.expect(false.B) dut.io.clearKeyBuffer.expect(false.B) dut.io.deq.valid.expect(false.B) dut.io.enq.ready.expect(false.B) - dut.io.bufferSelect.expect(0.U) } } - "Should not output deq.valid == true when clearing Key Buffer" in { + "Should output deq.valid == false when clearing Key Buffer" in { test(new KvTransfer(4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // set inputs to default dut.io.enq.bits.poke(0.U) @@ -519,6 +618,7 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.deq.ready.poke(true.B) dut.io.enq.ready.expect(true.B) dut.io.busy.expect(true.B) + dut.io.outputSelect.expect(true.B) dut.clock.step() @@ -557,6 +657,7 @@ class KvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { } else { dut.io.isOutputKey.expect(true.B) } + dut.io.outputSelect.expect(true.B) dut.clock.step() } @@ -578,6 +679,7 @@ class TopKvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.enq(i).bits.poke(0.U) dut.io.enq(i).valid.poke(false.B) } + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.incrKeyBufferPtr.expect(false.B) @@ -605,7 +707,7 @@ class TopKvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.io.enq(0).bits.poke(0xA.U) dut.clock.step() - // Start transfer of data + // Transfer a key chunk from 1st buffer dut.io.deq.ready.poke(true.B) dut.io.busy.expect(true.B) @@ -672,10 +774,8 @@ class TopKvTransferSpec extends AnyFreeSpec with ChiselScalatestTester { dut.clock.step() // check if all buffers are empty, need one cycle - dut.io.bufferSelect.expect(0.U) dut.io.busy.expect(true.B) dut.io.outputKeyOnly.expect(true.B) - dut.io.incrKeyBufferPtr.expect(false.B) dut.io.clearKeyBuffer.expect(false.B) dut.io.deq.valid.expect(false.B) diff --git a/src/test/scala/MergerSpec.scala b/src/test/scala/MergerSpec.scala index b01e8dd..dea9835 100644 --- a/src/test/scala/MergerSpec.scala +++ b/src/test/scala/MergerSpec.scala @@ -14,6 +14,7 @@ class MergerSpec extends AnyFreeSpec with ChiselScalatestTester { test(new Merger(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // reset Merger for a new comparison round dut.io.reset.poke(true.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.reset.poke(false.B) @@ -113,6 +114,7 @@ class MergerSpec extends AnyFreeSpec with ChiselScalatestTester { test(new Merger(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // reset Merger for a new comparison round dut.io.reset.poke(true.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.reset.poke(false.B) @@ -202,6 +204,7 @@ class MergerSpec extends AnyFreeSpec with ChiselScalatestTester { test(new Merger(busWidth = 4, numberOfBuffers = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => // reset Merger for a new comparison round dut.io.reset.poke(true.B) + dut.io.mask.poke("b1111".U) dut.clock.step() dut.io.reset.poke(false.B) diff --git a/src/test/scala/NextIndexSelectorSpec.scala b/src/test/scala/NextIndexSelectorSpec.scala new file mode 100644 index 0000000..fc6445e --- /dev/null +++ b/src/test/scala/NextIndexSelectorSpec.scala @@ -0,0 +1,40 @@ +package compaction_unit + +import chisel3._ +import chiseltest._ +import org.scalatest.freespec.AnyFreeSpec +import chisel3.experimental.BundleLiterals._ + + +class NextIndexSelectorSpec extends AnyFreeSpec with ChiselScalatestTester { + "Different inputs produce correct outputs" in { + test(new NextIndexSelector(n = 4)).withAnnotations(Seq(WriteVcdAnnotation)) { dut => + val testCases = Seq( + // mask, currentIndex, nextIndex, overflow + ("b1111", 0, 1, false), + ("b1111", 1, 2, false), + ("b1111", 2, 3, false), + ("b1111", 3, 0, true), + + ("b1001", 0, 3, false), + ("b0100", 2, 2, true), + ("b1000", 3, 3, true), + ("b0110", 2, 1, true), + ("b0110", 1, 2, false), + + // If mask is there, the last index is always selected + ("b0000", 0, 3, true), + ("b0000", 1, 3, true), + ("b0000", 2, 3, true), + ("b0000", 3, 3, true), + ) + + for ((mask, currentIndex, nextIndex, overflow) <- testCases) { + dut.io.mask.poke(mask.U) + dut.io.currentIndex.poke(currentIndex.U) + dut.io.nextIndex.expect(nextIndex.U) + dut.io.overflow.expect(overflow.B) + } + } + } +}