Non-Linear-Distortion-Module-FPGA/.gitignore at main · VRM21-Studios/Non-Linear-Distortion-Module-FPGA · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
# ============================================================================
# Vivado / FPGA Tool Artifacts
# ============================================================================

# Vivado projects
*.xpr
*.jou
*.log
*.str
*.zip

# Vivado generated folders
.vivado/
.ip_user_files/
.cache/
.hw/
.runs/
.sim/
.gen/
.tmp/
.srcs/
.bd/
.sdk/
.vitis/
.metadata/

# IP cache and checkpoints
*.dcp
*.xci
*.xcix
*.xsa
*.hwh
*.hwdef

# Reports
*.rpt
*.pb
*.xml
*.html

# ============================================================================
# Simulation Artifacts
# ============================================================================

# Waveforms
*.wdb
*.vcd
*.fsdb
*.shm
*.trn

# Compiled simulation outputs
xsim.dir/
work/
questa/
modelsim.ini

# Temporary simulation files
*.dat
*.tmp

# ============================================================================
# Software / Python Artifacts
# ============================================================================

# Python
__pycache__/
*.pyc
*.pyo
*.pyd
*.egg-info/
.venv/
venv/

# Jupyter
.ipynb_checkpoints/

# ============================================================================
# OS / Editor Noise
# ============================================================================

# Windows
Thumbs.db
desktop.ini

# macOS
.DS_Store

# Linux
*~

# Editors
.vscode/
.idea/

# ============================================================================
# Explicitly Tracked (DO NOT IGNORE)
# ============================================================================

# RTL source files
!rtl/**/*.v
!rtl/**/*.sv

# Testbenches
!tb/**/*.v
!tb/**/*.sv

# Documentation
!docs/**/*.md
!results/**/*.md

# Numerical validation data
!results/**/*.csv

# Scripts
!scripts/**/*.tcl

# License & README
!README.md
!LICENSE