[armv7] Add lifting for VCVT floating-point scalar variants

Author: galenbwill

arch/armv7/il.cpp

@@ -4936,18 +4936,31 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
 		case ARMV7_VCVT:
 			switch (instr.dataType)
 			{
+			// To integer cases
 			case DT_S32:
 			case DT_U32:
 				switch (instr.dataType2)
 				{
 				case DT_F32:
 				case DT_F64:
-					// ConditionExecute(il, instr.cond,
-					// 	il.SetRegister(get_register_size(op1.reg), op1.reg,
-					// 		il.FloatToInt(4, il.Register(get_register_size(op2.reg), op2.reg))));
-					ConditionExecute(il, instr.cond,
-						il.SetRegister(get_register_size(op1.reg), op1.reg,
-							il.FloatToInt(get_register_size(op1.reg), il.Register(get_register_size(op2.reg), op2.reg))));
+					ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg,
+						il.FloatToInt(get_register_size(op1.reg), il.RoundToInt(get_register_size(op2.reg),
+							il.Register(get_register_size(op2.reg), op2.reg)))));
+					break;
+				default:
+					break;
+				}
+				break;
+			// To float from integer cases
+			case DT_F32:
+			case DT_F64:
+				switch (instr.dataType2)
+				{
+				case DT_S32:
+				case DT_U32:
+					ConditionExecute(il, instr.cond, il.SetRegister(get_register_size(op1.reg), op1.reg,
+						il.IntToFloat(get_register_size(op1.reg),
+							il.Register(get_register_size(op2.reg), op2.reg))));
 					break;
 				default:
 					break;