@@ -2194,6 +2194,48 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
21942194
21952195 break ;
21962196 }
2197+ case MIPS_PADDUW:
2198+ {
2199+ for (int i = 0 ; i < 4 ; i++)
2200+ {
2201+ size_t offset = i * 32 ;
2202+ auto rs_segment = il.And (16 ,
2203+ il.LogicalShiftRight (
2204+ 16 ,
2205+ il.Register (16 , op2.reg ),
2206+ il.Const (4 , offset)
2207+ ),
2208+ il.Const (128 , 0xFFFFFFFF )
2209+ );
2210+ auto rt_segment = il.And (16 ,
2211+ il.LogicalShiftRight (
2212+ 16 ,
2213+ il.Register (16 , op3.reg ),
2214+ il.Const (4 , offset)
2215+ ),
2216+ il.Const (128 , 0xFFFFFFFF )
2217+ );
2218+
2219+ auto sum = il.Add (8 , rs_segment, rt_segment);
2220+
2221+ // This is a 4 byte add, but if the sum is greater than 0xFFFFFFFF, the result is 0xFFFFFFFF
2222+ // So we do an 8 bit add and and the result
2223+
2224+ auto saturated_sum = il.And (4 , sum, il.Const (4 , 0xFFFFFFFF ));
2225+
2226+ auto shifted_sum = il.ShiftLeft (16 , saturated_sum, il.Const (4 , offset));
2227+ if (i == 0 )
2228+ {
2229+ il.AddInstruction (il.SetRegister (16 , op1.reg , shifted_sum));
2230+ }
2231+ else
2232+ {
2233+ il.AddInstruction (il.SetRegister (16 , op1.reg , il.Or (16 , il.Register (16 , op1.reg ), shifted_sum)));
2234+ }
2235+ }
2236+
2237+ break ;
2238+ }
21972239
21982240 case MIPS_ADDR:
21992241 case MIPS_LDXC1:
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