Remove Architecture trait bound on LLIL related structures in Rust API

Author: emesare

arch/msp430/src/architecture.rs

@@ -194,7 +194,7 @@ impl Architecture for Msp430 {
         &self,
         data: &[u8],
         addr: u64,
-        il: &mut MutableLiftedILFunction<Self>,
+        il: &mut MutableLiftedILFunction,
     ) -> Option<(usize, bool)> {
         match msp430_asm::decode(data) {
             Ok(inst) => {
@@ -226,8 +226,8 @@ impl Architecture for Msp430 {
     fn flag_group_llil<'a>(
         &self,
         _group: Self::FlagGroup,
-        _il: &'a mut MutableLiftedILFunction<Self>,
-    ) -> Option<MutableLiftedILExpr<'a, Self, ValueExpr>> {
+        _il: &'a mut MutableLiftedILFunction,
+    ) -> Option<MutableLiftedILExpr<'a, ValueExpr>> {
         None
     }
 

arch/msp430/src/lift.rs

@@ -1,7 +1,6 @@
 use crate::architecture::offset_to_absolute;
 use crate::flag::{Flag, FlagWrite};
 use crate::register::Register;
-use crate::Msp430;
 
 use binaryninja::{architecture::FlagCondition, low_level_il::lifting::LowLevelILLabel};
 
@@ -164,11 +163,7 @@ macro_rules! conditional_jump {
     };
 }
 
-pub(crate) fn lift_instruction(
-    inst: &Instruction,
-    addr: u64,
-    il: &MutableLiftedILFunction<Msp430>,
-) {
+pub(crate) fn lift_instruction(inst: &Instruction, addr: u64, il: &MutableLiftedILFunction) {
     match inst {
         Instruction::Rrc(inst) => {
             let size = match inst.operand_width() {
@@ -628,8 +623,8 @@ pub(crate) fn lift_instruction(
 fn lift_source_operand<'a>(
     operand: &Operand,
     size: usize,
-    il: &'a MutableLiftedILFunction<Msp430>,
-) -> MutableLiftedILExpr<'a, Msp430, ValueExpr> {
+    il: &'a MutableLiftedILFunction,
+) -> MutableLiftedILExpr<'a, ValueExpr> {
     match operand {
         Operand::RegisterDirect(r) => il.reg(size, Register::try_from(*r as u32).unwrap()),
         Operand::Indexed((r, offset)) => il

arch/msp430/src/register.rs

@@ -1,7 +1,7 @@
 use binaryninja::architecture;
 use binaryninja::architecture::{ImplicitRegisterExtend, RegisterId};
 
-use binaryninja::low_level_il::LowLevelILRegister;
+use binaryninja::low_level_il::LowLevelILRegisterKind;
 use std::borrow::Cow;
 
 #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
@@ -134,8 +134,8 @@ impl architecture::RegisterInfo for Register {
     }
 }
 
-impl From<Register> for LowLevelILRegister<Register> {
+impl From<Register> for LowLevelILRegisterKind<Register> {
     fn from(register: Register) -> Self {
-        LowLevelILRegister::ArchReg(register)
+        LowLevelILRegisterKind::Arch(register)
     }
 }

arch/riscv/disasm/src/lib.rs

@@ -2331,7 +2331,7 @@ impl StandardExtension for ExtensionSupported {
     }
 }
 
-pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone  + Send + Sync {
+pub trait RiscVDisassembler: 'static + Debug + Sized + Copy + Clone + Send + Sync {
     type RegFile: RegFile;
     type MulDivExtension: StandardExtension;
     type AtomicExtension: StandardExtension;