@@ -44,7 +44,8 @@ use binaryninja::low_level_il::lifting::{
4444} ;
4545use binaryninja:: low_level_il:: {
4646 expression:: ExpressionHandler , instruction:: InstructionHandler , LowLevelILMutableExpression ,
47- LowLevelILMutableFunction , LowLevelILRegisterKind , LowLevelILRegularFunction ,
47+ LowLevelILMutableFunction , LowLevelILOperandIndex , LowLevelILRegisterKind ,
48+ LowLevelILRegularFunction ,
4849} ;
4950use riscv_dis:: {
5051 FloatReg , FloatRegType , Instr , IntRegType , Op , RegFile , Register as RiscVRegister ,
@@ -1117,12 +1118,12 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
11171118
11181119 let src_expr = il. add( max_width, rs1, l. imm( ) ) ;
11191120 let load_expr = il. load( size, src_expr)
1120- . with_source_operand( 1 ) ;
1121+ . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
11211122
11221123 match ( size < max_width, l. zx( ) ) {
11231124 ( false , _) => load_expr,
1124- ( true , true ) => il. zx( max_width, load_expr) . build ( ) ,
1125- ( true , false ) => il. sx( max_width, load_expr) . build ( ) ,
1125+ ( true , true ) => il. zx( max_width, load_expr) ,
1126+ ( true , false ) => il. sx( max_width, load_expr) ,
11261127 }
11271128 } ) ,
11281129 Op :: Store ( s) => {
@@ -1136,7 +1137,9 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
11361137 src = il. low_part ( size, src) . build ( ) ;
11371138 }
11381139
1139- il. store ( size, dest, src) . with_source_operand ( 1 ) . append ( ) ;
1140+ il. store ( size, dest, src)
1141+ . with_source_operand ( LowLevelILOperandIndex ( 1 ) )
1142+ . append ( ) ;
11401143 }
11411144
11421145 Op :: AddI ( i) => simple_i ! ( i, |rs1, imm| il. add( max_width, rs1, imm) ) ,
@@ -1459,11 +1462,11 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
14591462 Op :: Lr ( a) => simple_op ! ( a, no_discard {
14601463 let size = a. width( ) ;
14611464 let load_expr = il. load( size, Register :: from( a. rs1( ) ) )
1462- . with_source_operand( 1 ) ;
1465+ . with_source_operand( LowLevelILOperandIndex ( 1 ) ) ;
14631466
14641467 match size == max_width {
14651468 true => load_expr,
1466- false => il. sx( max_width, load_expr) . build ( ) ,
1469+ false => il. sx( max_width, load_expr) ,
14671470 }
14681471 } ) ,
14691472 Op :: Sc ( a) => {
@@ -1497,7 +1500,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
14971500
14981501 il. mark_label ( & mut t) ;
14991502 il. store ( size, Register :: from ( a. rs1 ( ) ) , Register :: from ( a. rs2 ( ) ) )
1500- . with_source_operand ( 2 )
1503+ . with_source_operand ( LowLevelILOperandIndex ( 2 ) )
15011504 . append ( ) ;
15021505
15031506 if new_false {
@@ -1539,10 +1542,12 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
15391542 let reg_with_address = alloc_reg ( rs1) ;
15401543 let reg_with_val = alloc_reg ( rs2) ;
15411544
1542- let mut load_expr = il. load ( size, Register :: from ( rs1) ) . with_source_operand ( 2 ) ;
1545+ let mut load_expr = il
1546+ . load ( size, Register :: from ( rs1) )
1547+ . with_source_operand ( LowLevelILOperandIndex ( 2 ) ) ;
15431548
15441549 if size < max_width {
1545- load_expr = il. sx ( max_width, load_expr) . build ( ) ;
1550+ load_expr = il. sx ( max_width, load_expr) ;
15461551 }
15471552
15481553 il. set_reg ( max_width, dest_reg, load_expr) . append ( ) ;
@@ -1571,7 +1576,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
15711576
15721577 let load_expr = il
15731578 . load ( m. width ( ) , il. add ( max_width, rs1, m. imm ( ) ) )
1574- . with_source_operand ( 1 ) ;
1579+ . with_source_operand ( LowLevelILOperandIndex ( 1 ) ) ;
15751580
15761581 il. set_reg ( m. width ( ) , rd, load_expr) . append ( ) ;
15771582 }
@@ -1582,7 +1587,7 @@ impl<D: RiscVDisassembler> Architecture for RiscVArch<D> {
15821587 let dest_expr = il. add ( max_width, rs1, m. imm ( ) ) ;
15831588
15841589 il. store ( m. width ( ) , dest_expr, il. reg ( m. width ( ) , rs2) )
1585- . with_source_operand ( 1 )
1590+ . with_source_operand ( LowLevelILOperandIndex ( 1 ) )
15861591 . append ( ) ;
15871592 }
15881593 Op :: Fmadd ( f) | Op :: Fmsub ( f) | Op :: Fnmadd ( f) | Op :: Fnmsub ( f) => {
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