Fix: PowerPC decode logic for Rx, Ry, Rz register

chedahub · plafosse · commit 623f07a2b44a · 2025-10-22T09:33:28.000-04:00
diff --git a/arch/powerpc/decode/vle16.c b/arch/powerpc/decode/vle16.c
@@ -335,17 +335,20 @@ static InstructionId Decode16Vle(uint16_t word16, uint32_t decodeFlags)
 }
 static uint16_t Get16Rx(uint16_t word16)
 {
-	return word16 & 0xf;
+	uint16_t rx = word16 & 0xf;
+	return rx + ((rx & 0x8) >> 3) * 16;
 }
 
 static uint16_t Get16Ry(uint16_t word16)
 {
-	return (word16 >> 4) & 0xf;
+	uint16_t ry = (word16 >> 4) & 0xf;
+	return ry + ((ry & 0x8) >> 3) * 16;
 }
 
 static uint16_t Get16Rz(uint16_t word16)
 {
-	return (word16 >> 4) & 0xf;
+	uint16_t rz = (word16 >> 4) & 0xf;
+	return rz + ((rz & 0x8) >> 3) * 16;
 }
 
 static void FillOperands16Vle(Instruction* instruction, uint16_t word16, uint64_t address, bool translate)

Original file line number	Diff line number	Diff line change
`@@ -335,17 +335,20 @@ static InstructionId Decode16Vle(uint16_t word16, uint32_t decodeFlags)`
`335`	`335`	`}`
`336`	`336`	`static uint16_t Get16Rx(uint16_t word16)`
`337`	`337`	`{`
`338`		`- return word16 & 0xf;`
	`338`	`+ uint16_t rx = word16 & 0xf;`
	`339`	`+ return rx + ((rx & 0x8) >> 3) * 16;`
`339`	`340`	`}`
`340`	`341`
`341`	`342`	`static uint16_t Get16Ry(uint16_t word16)`
`342`	`343`	`{`
`343`		`- return (word16 >> 4) & 0xf;`
	`344`	`+ uint16_t ry = (word16 >> 4) & 0xf;`
	`345`	`+ return ry + ((ry & 0x8) >> 3) * 16;`
`344`	`346`	`}`
`345`	`347`
`346`	`348`	`static uint16_t Get16Rz(uint16_t word16)`
`347`	`349`	`{`
`348`		`- return (word16 >> 4) & 0xf;`
	`350`	`+ uint16_t rz = (word16 >> 4) & 0xf;`
	`351`	`+ return rz + ((rz & 0x8) >> 3) * 16;`
`349`	`352`	`}`
`350`	`353`
`351`	`354`	`static void FillOperands16Vle(Instruction* instruction, uint16_t word16, uint64_t address, bool translate)`