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galenbwillgalenbwill
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WIP [mips] Fixing PR for r5900: lots more lifting of v* instructions
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‎arch/mips/il.cpp‎

Lines changed: 108 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3647,13 +3647,46 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
36473647
il.AddInstruction(SetRegisterOrNop(il, 16, 16, op1.reg, il.Register(16, LLIL_TEMP(0))));
36483648
break;
36493649
}
3650-
/*
3651-
Opcode "pcgth" is unimplemented (LLIL)
3652-
Opcode "ppacb" is unimplemented (LLIL)
3653-
Opcode "psllh" is unimplemented (LLIL)
3654-
Opcode "psrah" is unimplemented (LLIL)
3655-
Opcode "psrlh" is unimplemented (LLIL)
3656-
*/
3650+
3651+
// case MIPS_PEXCH:
3652+
case MIPS_PEXCW:
3653+
{
3654+
il.AddInstruction(il.SetRegister(16, op1.reg,
3655+
il.Or(16,
3656+
il.Xor(16, il.Register(16, op2.reg),
3657+
il.And(16, il.Register(16, op2.reg),
3658+
il.ShiftLeft(16, il.Const(16, 0xFFFFFFFFFFFFFFFF), il.Const(16, 32)))),
3659+
il.Or(16,
3660+
il.ShiftLeft(16,
3661+
il.And(16, il.LogicalShiftRight(64, il.Register(16, op2.reg), il.Const(16, 64)),
3662+
il.Const(16, 0xFFFFFFFF)),
3663+
il.Const(16, 32)),
3664+
il.ShiftLeft(16,
3665+
il.And(16, il.LogicalShiftRight(64, il.Register(16, op2.reg), il.Const(16, 32)),
3666+
il.Const(16, 0xFFFFFFFF)),
3667+
il.Const(16, 64))
3668+
))));
3669+
break;
3670+
}
3671+
case MIPS_PEXEW:
3672+
{
3673+
il.AddInstruction(il.SetRegister(16, op1.reg,
3674+
il.Or(16,
3675+
il.Xor(16, il.Register(16, op2.reg),
3676+
il.And(16, il.Register(16, op2.reg),
3677+
il.ShiftLeft(16, il.Const(16, 0xFFFFFFFFFFFFFFFF), il.Const(16, 32)))),
3678+
il.Or(16,
3679+
il.ShiftLeft(16,
3680+
il.And(16, il.LogicalShiftRight(64, il.Register(16, op2.reg), il.Const(16, 64)),
3681+
il.Const(16, 0xFFFFFFFF)),
3682+
il.Const(16, 32)),
3683+
il.ShiftLeft(16,
3684+
il.And(16, il.LogicalShiftRight(64, il.Register(16, op2.reg), il.Const(16, 32)),
3685+
il.Const(16, 0xFFFFFFFF)),
3686+
il.Const(16, 64))
3687+
))));
3688+
break;
3689+
}
36573690

36583691

36593692
case MIPS_CTC1:
@@ -3835,7 +3868,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
38353868
case MIPS_PREVH:
38363869
case MIPS_PMULTH:
38373870
case MIPS_PDIVBW:
3838-
case MIPS_PEXEW:
3871+
// case MIPS_PEXEW:
38393872
case MIPS_PROT3W:
38403873
case MIPS_PMADDUW:
38413874
case MIPS_PSRAVW:
@@ -3847,9 +3880,9 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
38473880
// case MIPS_PCPYUD:
38483881
// case MIPS_POR:
38493882
// case MIPS_PNOR:
3850-
case MIPS_PEXCH:
3883+
// case MIPS_PEXCH:
38513884
// case MIPS_PCPYH:
3852-
case MIPS_PEXCW:
3885+
// case MIPS_PEXCW:
38533886
// case MIPS_BC0F:
38543887
// case MIPS_BC0T:
38553888
// case MIPS_BC0FL:
@@ -4208,6 +4241,32 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
42084241
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VACC_W - REG_VACC, il.FloatAdd(4, il.Register(4, op2.reg + REG_VACC_W - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg + REG_VF0_W)))));
42094242
break;
42104243
}
4244+
case MIPS_VMSUB:
4245+
{
4246+
unsigned char dest = op1.reg;
4247+
if (dest & (1 << 3))
4248+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_X, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_X - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_X), il.Register(4, op4.reg + REG_VF0_X)))));
4249+
if (dest & (1 << 2))
4250+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Y, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Y - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Y), il.Register(4, op4.reg + REG_VF0_Y)))));
4251+
if (dest & (1 << 1))
4252+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Z, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Z - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Z), il.Register(4, op4.reg + REG_VF0_Z)))));
4253+
if (dest & (1 << 0))
4254+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_W, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_W - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg + REG_VF0_W)))));
4255+
break;
4256+
}
4257+
case MIPS_VMSUBA:
4258+
{
4259+
unsigned char dest = op1.reg;
4260+
if (dest & (1 << 3))
4261+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VACC_X - REG_VACC, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_X - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_X), il.Register(4, op4.reg + REG_VF0_X)))));
4262+
if (dest & (1 << 2))
4263+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VACC_Y - REG_VACC, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Y - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Y), il.Register(4, op4.reg + REG_VF0_Y)))));
4264+
if (dest & (1 << 1))
4265+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VACC_Z - REG_VACC, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Z - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Z), il.Register(4, op4.reg + REG_VF0_Z)))));
4266+
if (dest & (1 << 0))
4267+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VACC_W - REG_VACC, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_W - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg + REG_VF0_W)))));
4268+
break;
4269+
}
42114270
case MIPS_VMADDAx:
42124271
case MIPS_VMADDAy:
42134272
case MIPS_VMADDAz:
@@ -4242,6 +4301,23 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
42424301
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_W, il.FloatAdd(4, il.Register(4, REG_VACC_W), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg + bc)))));
42434302
break;
42444303
}
4304+
case MIPS_VMSUBx:
4305+
case MIPS_VMSUBy:
4306+
case MIPS_VMSUBz:
4307+
case MIPS_VMSUBw:
4308+
{
4309+
unsigned char dest = op1.reg;
4310+
auto bc = REG_VF0_X + (op4.immediate - 1) * 33;
4311+
if (dest & (1 << 3))
4312+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_X, il.FloatSub(4, il.Register(4, REG_VACC_X), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_X), il.Register(4, op4.reg + bc)))));
4313+
if (dest & (1 << 2))
4314+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Y, il.FloatSub(4, il.Register(4, REG_VACC_Y), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Y), il.Register(4, op4.reg + bc)))));
4315+
if (dest & (1 << 1))
4316+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Z, il.FloatSub(4, il.Register(4, REG_VACC_Z), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Z), il.Register(4, op4.reg + bc)))));
4317+
if (dest & (1 << 0))
4318+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_W, il.FloatSub(4, il.Register(4, REG_VACC_W), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg + bc)))));
4319+
break;
4320+
}
42454321
case MIPS_VMADDq:
42464322
case MIPS_VMADDi:
42474323
{
@@ -4256,6 +4332,20 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
42564332
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_W, il.FloatAdd(4, il.Register(4, op2.reg + REG_VACC_W - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg)))));
42574333
break;
42584334
}
4335+
case MIPS_VMSUBq:
4336+
case MIPS_VMSUBi:
4337+
{
4338+
unsigned char dest = op1.reg;
4339+
if (dest & (1 << 3))
4340+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_X, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_X - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_X), il.Register(4, op4.reg)))));
4341+
if (dest & (1 << 2))
4342+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Y, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Y - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Y), il.Register(4, op4.reg)))));
4343+
if (dest & (1 << 1))
4344+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_Z, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_Z - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_Z), il.Register(4, op4.reg)))));
4345+
if (dest & (1 << 0))
4346+
il.AddInstruction(il.SetRegister(4, op2.reg + REG_VF0_W, il.FloatSub(4, il.Register(4, op2.reg + REG_VACC_W - REG_VACC), il.FloatMult(4, il.Register(4, op3.reg + REG_VF0_W), il.Register(4, op4.reg)))));
4347+
break;
4348+
}
42594349
case MIPS_VDIV:
42604350
{
42614351
il.AddInstruction(il.SetRegister(4, op1.reg, il.FloatDiv(4, il.Register(4, op2.reg + REG_VF0_X + (op2.immediate) * 33), il.Register(4, op3.reg + REG_VF0_X + (op3.immediate) * 33))));
@@ -4347,9 +4437,16 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
43474437
break;
43484438
}
43494439

4440+
case MIPS_VIADD:
4441+
case MIPS_VIADDI:
4442+
{
4443+
il.AddInstruction(il.SetRegister(2, op1.reg, il.Add(2, il.Register(2, op2.reg), ReadILOperand(il, instr, 3, 2, 1))));
4444+
break;
4445+
}
43504446

43514447
// case MIPS_VDIV:
4352-
case MIPS_VIADD:
4448+
// case MIPS_VIADD:
4449+
// case MIPS_VIADDI:
43534450
case MIPS_VIOR:
43544451
// case MIPS_VMADD:
43554452
// case MIPS_VMADDAx:

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