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galenbwillgalenbwill
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[aarch64] Updating Aarch64 system registers to 2024-12 spec, fix MSR/MRS lifting to use ReadMSR/WriteMSR intrinsics that take enums, removing the sysregs from the register list of the architecture
* sysregs are no longer registers, add enum for TLBI and AT operands * add erroneously missing cases for unsupported encodings, add enum for DC operands
1 parent 8093106 commit b095215

18 files changed

+9294
-565
lines changed

‎arch/arm64/CMakeLists.txt‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,8 @@ file(GLOB SOURCES
88
*.h
99
disassembler/decode.c
1010
disassembler/format.c
11-
disassembler/sysregs.c
11+
disassembler/sysregs_gen.c
12+
disassembler/sysregs_fmt_gen.c
1213
disassembler/regs.c
1314
disassembler/encodings_dec.c
1415
disassembler/encodings_fmt.c
@@ -21,6 +22,8 @@ file(GLOB SOURCES
2122
disassembler/decode_scratchpad.c
2223
disassembler/*.h)
2324

25+
list(FILTER SOURCES EXCLUDE REGEX "sysregs\\.(h|cpp)$")
26+
2427
if(DEMO)
2528
add_library(${PROJECT_NAME} STATIC ${SOURCES})
2629
else()

‎arch/arm64/arch_arm64.cpp‎

Lines changed: 86 additions & 176 deletions
Large diffs are not rendered by default.

‎arch/arm64/disassembler/decode.h‎

Lines changed: 265 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,8 @@
1010

1111
#include "encodings_dec.h"
1212
#include "regs.h"
13-
#include "sysregs.h"
13+
#include "sysregs_gen.h"
14+
#include "sysregs_fmt_gen.h"
1415

1516
#ifdef _MSC_VER
1617
#undef REG_NONE // collides with winnt's define
@@ -112,6 +113,21 @@ enum SliceIndicator
112113
#define FPCR_GET_DZE(X) SLICE(X, 9, 9)
113114
#define FPCR_GET_IOE(X) SLICE(X, 8, 8)
114115

116+
//-----------------------------------------------------------------------------
117+
// <tlbi_op>: TLBI operands
118+
//-----------------------------------------------------------------------------
119+
#define TLBI_OP(op1, crn, crm, op2) (((op1 & 7) << 11) | ((crn & 0xF) << 7) | ((crm & 0xF) << 3) | ((op2) & 7))
120+
121+
//-----------------------------------------------------------------------------
122+
// <at_op>: AT operands
123+
//-----------------------------------------------------------------------------
124+
#define AT_OP(op1, crm, op2) (TLBI_OP(op1, 7, crm, op2))
125+
126+
//-----------------------------------------------------------------------------
127+
// <dc_op>: DC operands
128+
//-----------------------------------------------------------------------------
129+
#define DC_OP(op1, crm, op2) (TLBI_OP(op1, 7, crm, op2))
130+
115131
//-----------------------------------------------------------------------------
116132
// disassembly context (INPUT into disassembler)
117133
//-----------------------------------------------------------------------------
@@ -497,6 +513,251 @@ enum FlagEffect
497513
FLAGEFFECT_SETS_FLOAT=3 // sets flags after float comparison
498514
};
499515

516+
enum ImplSpec
517+
{
518+
OP0 = 0,
519+
OP1 = 1,
520+
CRN = 2,
521+
CRM = 3,
522+
OP2 = 4
523+
};
524+
525+
enum ATOp
526+
{
527+
AT_OP_INVALID=-1,
528+
AT_OP_S1E1R=AT_OP(0b000, 0b1000, 0b000),
529+
AT_OP_S1E1W=AT_OP(0b000, 0b1000, 0b001),
530+
AT_OP_S1E0R=AT_OP(0b000, 0b1000, 0b010),
531+
AT_OP_S1E0W=AT_OP(0b000, 0b1000, 0b011),
532+
AT_OP_S1E1RP=AT_OP(0b000, 0b1001, 0b000),
533+
AT_OP_S1E1WP=AT_OP(0b000, 0b1001, 0b001),
534+
AT_OP_S1E1A=AT_OP(0b000, 0b1001, 0b010),
535+
AT_OP_S1E2R=AT_OP(0b100, 0b1000, 0b000),
536+
AT_OP_S1E2W=AT_OP(0b100, 0b1000, 0b001),
537+
AT_OP_S12E1R=AT_OP(0b100, 0b1000, 0b100),
538+
AT_OP_S12E1W=AT_OP(0b100, 0b1000, 0b101),
539+
AT_OP_S12E0R=AT_OP(0b100, 0b1000, 0b110),
540+
AT_OP_S12E0W=AT_OP(0b100, 0b1000, 0b111),
541+
AT_OP_S1E2A=AT_OP(0b100, 0b1001, 0b010),
542+
AT_OP_S1E3R=AT_OP(0b110, 0b1000, 0b000),
543+
AT_OP_S1E3W=AT_OP(0b110, 0b1000, 0b001),
544+
AT_OP_S1E3A=AT_OP(0b110, 0b1001, 0b010),
545+
};
546+
547+
enum TlbiOp
548+
{
549+
TLBI_INVALID=-1,
550+
TLBI_VMALLE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b000),
551+
TLBI_VAE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b001),
552+
TLBI_ASIDE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b010),
553+
TLBI_VAAE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b011),
554+
TLBI_VALE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b101),
555+
TLBI_VAALE1OS=TLBI_OP(0b000, 0b1000, 0b0001, 0b111),
556+
TLBI_RVAE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b001),
557+
TLBI_RVAAE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b011),
558+
TLBI_RVALE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b101),
559+
TLBI_RVAALE1IS=TLBI_OP(0b000, 0b1000, 0b0010, 0b111),
560+
TLBI_VMALLE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b000),
561+
TLBI_VAE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b001),
562+
TLBI_ASIDE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b010),
563+
TLBI_VAAE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b011),
564+
TLBI_VALE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b101),
565+
TLBI_VAALE1IS=TLBI_OP(0b000, 0b1000, 0b0011, 0b111),
566+
TLBI_RVAE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b001),
567+
TLBI_RVAAE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b011),
568+
TLBI_RVALE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b101),
569+
TLBI_RVAALE1OS=TLBI_OP(0b000, 0b1000, 0b0101, 0b111),
570+
TLBI_RVAE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b001),
571+
TLBI_RVAAE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b011),
572+
TLBI_RVALE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b101),
573+
TLBI_RVAALE1=TLBI_OP(0b000, 0b1000, 0b0110, 0b111),
574+
TLBI_VMALLE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b000),
575+
TLBI_VAE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b001),
576+
TLBI_ASIDE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b010),
577+
TLBI_VAAE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b011),
578+
TLBI_VALE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b101),
579+
TLBI_VAALE1=TLBI_OP(0b000, 0b1000, 0b0111, 0b111),
580+
TLBI_VMALLE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b000),
581+
TLBI_VAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b001),
582+
TLBI_ASIDE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b010),
583+
TLBI_VAAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b011),
584+
TLBI_VALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b101),
585+
TLBI_VAALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0001, 0b111),
586+
TLBI_RVAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b001),
587+
TLBI_RVAAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b011),
588+
TLBI_RVALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b101),
589+
TLBI_RVAALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0010, 0b111),
590+
TLBI_VMALLE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b000),
591+
TLBI_VAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b001),
592+
TLBI_ASIDE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b010),
593+
TLBI_VAAE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b011),
594+
TLBI_VALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b101),
595+
TLBI_VAALE1ISNXS=TLBI_OP(0b000, 0b1001, 0b0011, 0b111),
596+
TLBI_RVAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b001),
597+
TLBI_RVAAE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b011),
598+
TLBI_RVALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b101),
599+
TLBI_RVAALE1OSNXS=TLBI_OP(0b000, 0b1001, 0b0101, 0b111),
600+
TLBI_RVAE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b001),
601+
TLBI_RVAAE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b011),
602+
TLBI_RVALE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b101),
603+
TLBI_RVAALE1NXS=TLBI_OP(0b000, 0b1001, 0b0110, 0b111),
604+
TLBI_VMALLE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b000),
605+
TLBI_VAE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b001),
606+
TLBI_ASIDE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b010),
607+
TLBI_VAAE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b011),
608+
TLBI_VALE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b101),
609+
TLBI_VAALE1NXS=TLBI_OP(0b000, 0b1001, 0b0111, 0b111),
610+
TLBI_IPAS2E1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b001),
611+
TLBI_RIPAS2E1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b010),
612+
TLBI_IPAS2LE1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b101),
613+
TLBI_RIPAS2LE1IS=TLBI_OP(0b100, 0b1000, 0b0000, 0b110),
614+
TLBI_ALLE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b000),
615+
TLBI_VAE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b001),
616+
TLBI_ALLE1OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b100),
617+
TLBI_VALE2OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b101),
618+
TLBI_VMALLS12E1OS=TLBI_OP(0b100, 0b1000, 0b0001, 0b110),
619+
TLBI_RVAE2IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b001),
620+
TLBI_VMALLWS2E1IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b010),
621+
TLBI_RVALE2IS=TLBI_OP(0b100, 0b1000, 0b0010, 0b101),
622+
TLBI_ALLE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b000),
623+
TLBI_VAE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b001),
624+
TLBI_ALLE1IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b100),
625+
TLBI_VALE2IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b101),
626+
TLBI_VMALLS12E1IS=TLBI_OP(0b100, 0b1000, 0b0011, 0b110),
627+
TLBI_IPAS2E1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b000),
628+
TLBI_IPAS2E1=TLBI_OP(0b100, 0b1000, 0b0100, 0b001),
629+
TLBI_RIPAS2E1=TLBI_OP(0b100, 0b1000, 0b0100, 0b010),
630+
TLBI_RIPAS2E1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b011),
631+
TLBI_IPAS2LE1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b100),
632+
TLBI_IPAS2LE1=TLBI_OP(0b100, 0b1000, 0b0100, 0b101),
633+
TLBI_RIPAS2LE1=TLBI_OP(0b100, 0b1000, 0b0100, 0b110),
634+
TLBI_RIPAS2LE1OS=TLBI_OP(0b100, 0b1000, 0b0100, 0b111),
635+
TLBI_RVAE2OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b001),
636+
TLBI_VMALLWS2E1OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b010),
637+
TLBI_RVALE2OS=TLBI_OP(0b100, 0b1000, 0b0101, 0b101),
638+
TLBI_RVAE2=TLBI_OP(0b100, 0b1000, 0b0110, 0b001),
639+
TLBI_VMALLWS2E1=TLBI_OP(0b100, 0b1000, 0b0110, 0b010),
640+
TLBI_RVALE2=TLBI_OP(0b100, 0b1000, 0b0110, 0b101),
641+
TLBI_ALLE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b000),
642+
TLBI_VAE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b001),
643+
TLBI_ALLE1=TLBI_OP(0b100, 0b1000, 0b0111, 0b100),
644+
TLBI_VALE2=TLBI_OP(0b100, 0b1000, 0b0111, 0b101),
645+
TLBI_VMALLS12E1=TLBI_OP(0b100, 0b1000, 0b0111, 0b110),
646+
TLBI_IPAS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b001),
647+
TLBI_RIPAS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b010),
648+
TLBI_IPAS2LE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b101),
649+
TLBI_RIPAS2LE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0000, 0b110),
650+
TLBI_ALLE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b000),
651+
TLBI_VAE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b001),
652+
TLBI_ALLE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b100),
653+
TLBI_VALE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b101),
654+
TLBI_VMALLS12E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0001, 0b110),
655+
TLBI_RVAE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b001),
656+
TLBI_VMALLWS2E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b010),
657+
TLBI_RVALE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0010, 0b101),
658+
TLBI_ALLE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b000),
659+
TLBI_VAE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b001),
660+
TLBI_ALLE1ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b100),
661+
TLBI_VALE2ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b101),
662+
TLBI_VMALLS12E1ISNXS=TLBI_OP(0b100, 0b1001, 0b0011, 0b110),
663+
TLBI_IPAS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b000),
664+
TLBI_IPAS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b001),
665+
TLBI_RIPAS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b010),
666+
TLBI_RIPAS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b011),
667+
TLBI_IPAS2LE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b100),
668+
TLBI_IPAS2LE1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b101),
669+
TLBI_RIPAS2LE1NXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b110),
670+
TLBI_RIPAS2LE1OSNXS=TLBI_OP(0b100, 0b1001, 0b0100, 0b111),
671+
TLBI_RVAE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b001),
672+
TLBI_VMALLWS2E1OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b010),
673+
TLBI_RVALE2OSNXS=TLBI_OP(0b100, 0b1001, 0b0101, 0b101),
674+
TLBI_RVAE2NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b001),
675+
TLBI_VMALLWS2E1NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b010),
676+
TLBI_RVALE2NXS=TLBI_OP(0b100, 0b1001, 0b0110, 0b101),
677+
TLBI_ALLE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b000),
678+
TLBI_VAE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b001),
679+
TLBI_ALLE1NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b100),
680+
TLBI_VALE2NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b101),
681+
TLBI_VMALLS12E1NXS=TLBI_OP(0b100, 0b1001, 0b0111, 0b110),
682+
TLBI_ALLE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b000),
683+
TLBI_VAE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b001),
684+
TLBI_PAALLOS=TLBI_OP(0b110, 0b1000, 0b0001, 0b100),
685+
TLBI_VALE3OS=TLBI_OP(0b110, 0b1000, 0b0001, 0b101),
686+
TLBI_RVAE3IS=TLBI_OP(0b110, 0b1000, 0b0010, 0b001),
687+
TLBI_RVALE3IS=TLBI_OP(0b110, 0b1000, 0b0010, 0b101),
688+
TLBI_ALLE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b000),
689+
TLBI_VAE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b001),
690+
TLBI_VALE3IS=TLBI_OP(0b110, 0b1000, 0b0011, 0b101),
691+
TLBI_RPAOS=TLBI_OP(0b110, 0b1000, 0b0100, 0b011),
692+
TLBI_RPALOS=TLBI_OP(0b110, 0b1000, 0b0100, 0b111),
693+
TLBI_RVAE3OS=TLBI_OP(0b110, 0b1000, 0b0101, 0b001),
694+
TLBI_RVALE3OS=TLBI_OP(0b110, 0b1000, 0b0101, 0b101),
695+
TLBI_RVAE3=TLBI_OP(0b110, 0b1000, 0b0110, 0b001),
696+
TLBI_RVALE3=TLBI_OP(0b110, 0b1000, 0b0110, 0b101),
697+
TLBI_ALLE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b000),
698+
TLBI_VAE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b001),
699+
TLBI_PAALL=TLBI_OP(0b110, 0b1000, 0b0111, 0b100),
700+
TLBI_VALE3=TLBI_OP(0b110, 0b1000, 0b0111, 0b101),
701+
TLBI_ALLE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b000),
702+
TLBI_VAE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b001),
703+
TLBI_VALE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0001, 0b101),
704+
TLBI_RVAE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0010, 0b001),
705+
TLBI_RVALE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0010, 0b101),
706+
TLBI_ALLE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b000),
707+
TLBI_VAE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b001),
708+
TLBI_VALE3ISNXS=TLBI_OP(0b110, 0b1001, 0b0011, 0b101),
709+
TLBI_RVAE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0101, 0b001),
710+
TLBI_RVALE3OSNXS=TLBI_OP(0b110, 0b1001, 0b0101, 0b101),
711+
TLBI_RVAE3NXS=TLBI_OP(0b110, 0b1001, 0b0110, 0b001),
712+
TLBI_RVALE3NXS=TLBI_OP(0b110, 0b1001, 0b0110, 0b101),
713+
TLBI_ALLE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b000),
714+
TLBI_VAE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b001),
715+
TLBI_VALE3NXS=TLBI_OP(0b110, 0b1001, 0b0111, 0b101),
716+
};
717+
718+
enum DCOp
719+
{
720+
DC_OP_INVALID=-1,
721+
DC_OP_IVAC=DC_OP(0b000, 0b0110, 0b001),
722+
DC_OP_ISW=DC_OP(0b000, 0b0110, 0b010),
723+
DC_OP_IGVAC=DC_OP(0b000, 0b0110, 0b011),
724+
DC_OP_IGSW=DC_OP(0b000, 0b0110, 0b100),
725+
DC_OP_IGDVAC=DC_OP(0b000, 0b0110, 0b101),
726+
DC_OP_IGDSW=DC_OP(0b000, 0b0110, 0b110),
727+
DC_OP_CSW=DC_OP(0b000, 0b1010, 0b010),
728+
DC_OP_CGSW=DC_OP(0b000, 0b1010, 0b100),
729+
DC_OP_CGDSW=DC_OP(0b000, 0b1010, 0b110),
730+
DC_OP_CISW=DC_OP(0b000, 0b1110, 0b010),
731+
DC_OP_CIGSW=DC_OP(0b000, 0b1110, 0b100),
732+
DC_OP_CIGDSW=DC_OP(0b000, 0b1110, 0b110),
733+
DC_OP_CIVAPS=DC_OP(0b000, 0b1111, 0b001),
734+
DC_OP_CIGDVAPS=DC_OP(0b000, 0b1111, 0b101),
735+
DC_OP_ZVA=DC_OP(0b011, 0b0100, 0b001),
736+
DC_OP_GVA=DC_OP(0b011, 0b0100, 0b011),
737+
DC_OP_GZVA=DC_OP(0b011, 0b0100, 0b100),
738+
DC_OP_CVAC=DC_OP(0b011, 0b1010, 0b001),
739+
DC_OP_CGVAC=DC_OP(0b011, 0b1010, 0b011),
740+
DC_OP_CGDVAC=DC_OP(0b011, 0b1010, 0b101),
741+
DC_OP_CVAOC=DC_OP(0b011, 0b1011, 0b000),
742+
DC_OP_CVAU=DC_OP(0b011, 0b1011, 0b001),
743+
DC_OP_CGDVAOC=DC_OP(0b011, 0b1011, 0b111),
744+
DC_OP_CVAP=DC_OP(0b011, 0b1100, 0b001),
745+
DC_OP_CGVAP=DC_OP(0b011, 0b1100, 0b011),
746+
DC_OP_CGDVAP=DC_OP(0b011, 0b1100, 0b101),
747+
DC_OP_CVADP=DC_OP(0b011, 0b1101, 0b001),
748+
DC_OP_CGVADP=DC_OP(0b011, 0b1101, 0b011),
749+
DC_OP_CGDVADP=DC_OP(0b011, 0b1101, 0b101),
750+
DC_OP_CIVAC=DC_OP(0b011, 0b1110, 0b001),
751+
DC_OP_CIGVAC=DC_OP(0b011, 0b1110, 0b011),
752+
DC_OP_CIGDVAC=DC_OP(0b011, 0b1110, 0b101),
753+
DC_OP_CIVAOC=DC_OP(0b011, 0b1111, 0b000),
754+
DC_OP_CIGDVAOC=DC_OP(0b011, 0b1111, 0b111),
755+
DC_OP_CIPAE=DC_OP(0b100, 0b1110, 0b000),
756+
DC_OP_CIGDPAE=DC_OP(0b100, 0b1110, 0b111),
757+
DC_OP_CIPAPA=DC_OP(0b110, 0b1110, 0b001),
758+
DC_OP_CIGDPAPA=DC_OP(0b110, 0b1110, 0b101),
759+
};
760+
500761
#ifndef __cplusplus
501762
typedef enum SystemReg SystemReg;
502763
typedef enum OperandClass OperandClass;
@@ -507,6 +768,8 @@ typedef enum Operation Operation;
507768
typedef enum Group Group;
508769
typedef enum ArrangementSpec ArrangementSpec;
509770
typedef enum SliceIndicator SliceIndicator;
771+
typedef enum ImplSpec ImplSpec;
772+
typedef enum TlbiOp TlbiOp;
510773
#endif
511774

512775
#define MAX_REGISTERS 5
@@ -574,6 +837,7 @@ extern "C"
574837

575838
int aarch64_decompose(uint32_t instructionValue, Instruction* instr, uint64_t address);
576839
size_t get_register_size(enum Register);
840+
// const char* tlbi_op(int32_t op);
577841

578842
#ifdef __cplusplus
579843
}

‎arch/arm64/disassembler/decode2.c‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27518,7 +27518,8 @@ int SYS(context *ctx, Instruction *instr)
2751827518
if(ctx->CRn==7 && SysOp(ctx->op1,7,ctx->CRm,ctx->op2)==Sys_DC) return DC_SYS(ctx, instr);
2751927519
if(ctx->op1==3 && ctx->CRn==7 && ctx->CRm==3 && ctx->op2==5) return DVP_SYS(ctx, instr);
2752027520
if(ctx->CRn==7 && SysOp(ctx->op1,7,ctx->CRm,ctx->op2)==Sys_IC) return IC_SYS(ctx, instr);
27521-
if(ctx->CRn==8 && SysOp(ctx->op1,8,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr);
27521+
// if(ctx->CRn==8 && SysOp(ctx->op1,8,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr);
27522+
if(((ctx->CRn&14)==8) && SysOp(ctx->op1,ctx->CRn,ctx->CRm,ctx->op2)==Sys_TLBI) return TLBI_SYS(ctx, instr);
2752227523
OK(ENC_SYS_CR_SYSTEMINSTRS);
2752327524
}
2752427525
return rc;
@@ -27666,8 +27667,10 @@ int TLBI_SYS(context *ctx, Instruction *instr)
2766627667
{
2766727668
int rc = DECODE_STATUS_UNMATCHED;
2766827669
/* class iclass_system */
27669-
/* 1101010100|L=0|op0=01|op1=xxx|CRn=1000|CRm=xxxx|op2=xxx|Rt=xxxxx */
27670-
if((INSWORD & 0xFFF8F000)==0xD5088000) {
27670+
// /* 1101010100|L=0|op0=01|op1=xxx|CRn=1000|CRm=xxxx|op2=xxx|Rt=xxxxx */
27671+
// if((INSWORD & 0xFFF8F000)==0xD5088000) {
27672+
/* 110|101|0100|L=0|01|op1=xxx|CRn=100x|CRm=xxxx|op2=xxx|Rt=xxxxx */
27673+
if((INSWORD & 0xFFF8E000)==0xD5088000) {
2767127674
decode_fields32(ENC_TLBI_SYS_CR_SYSTEMINSTRS, ctx, instr);
2767227675
OK(ENC_TLBI_SYS_CR_SYSTEMINSTRS);
2767327676
}

‎arch/arm64/disassembler/decode_fields32.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1626,6 +1626,7 @@ void decode_fields32(enum ENCODING enc, context *ctx, Instruction *instr)
16261626
case ENC_XAFLAG_M_PSTATE:
16271627
case ENC_XPACLRI_HI_HINTS:
16281628
case ENC_YIELD_HI_HINTS:
1629+
//['19:1101010100000:1101010100000', '16:op1:011', '12:0100:0100', '8:CRm:0111', '5:op2:110', '0:Rt:11111']
16291630
// xxxxxxxxxx|L=x|op0=xx|op1=xxx|CRn=xxxx|CRm=xxxx|op2=xxx|Rt=xxxxx
16301631
ctx->L = (insword>>21)&1;
16311632
ctx->op0 = (insword>>19)&3;

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