Skip to content

Commit bb8270f

Browse files
emesareemesare
committed
[Rust] Add missing ADD_OVERFLOW, TEST_BIT and LLIL_REG_STACK_FREE_REG low level IL expressions
1 parent b145f11 commit bb8270f

File tree

2 files changed

+67
-22
lines changed

2 files changed

+67
-22
lines changed

‎rust/src/low_level_il/expression.rs‎

Lines changed: 31 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -272,12 +272,14 @@ where
272272
ExternPtr(Operation<'func, M, F, operation::Extern>),
273273

274274
RegStackPop(Operation<'func, M, F, operation::RegStackPop>),
275+
RegStackFreeReg(Operation<'func, M, F, operation::RegStackPop>),
275276

276277
CallOutputSsa(Operation<'func, M, F, operation::CallOutputSsa>),
277278
CallParamSsa(Operation<'func, M, F, operation::CallParamSsa>),
278279
CallStackSsa(Operation<'func, M, F, operation::CallStackSsa>),
279280

280281
Add(Operation<'func, M, F, operation::BinaryOp>),
282+
AddOverflow(Operation<'func, M, F, operation::BinaryOp>),
281283
Adc(Operation<'func, M, F, operation::BinaryOpCarry>),
282284
Sub(Operation<'func, M, F, operation::BinaryOp>),
283285
Sbb(Operation<'func, M, F, operation::BinaryOpCarry>),
@@ -330,7 +332,7 @@ where
330332
CmpSgt(Operation<'func, M, F, operation::Condition>),
331333
CmpUgt(Operation<'func, M, F, operation::Condition>),
332334

333-
//TestBit(Operation<'func, M, F, operation::TestBit>), // TODO
335+
TestBit(Operation<'func, M, F, operation::BinaryOp>),
334336
BoolToInt(Operation<'func, M, F, operation::UnaryOp>),
335337

336338
Fadd(Operation<'func, M, F, operation::BinaryOp>),
@@ -361,7 +363,6 @@ where
361363

362364
SeparateParamListSsa(Operation<'func, M, F, operation::SeparateParamListSsa>),
363365

364-
// TODO ADD_OVERFLOW
365366
Unimpl(Operation<'func, M, F, operation::NoArgs>),
366367
UnimplMem(Operation<'func, M, F, operation::UnimplMem>),
367368

@@ -418,6 +419,9 @@ where
418419
LLIL_REG_STACK_POP => {
419420
LowLevelILExpressionKind::RegStackPop(Operation::new(function, op, index))
420421
}
422+
LLIL_REG_STACK_FREE_REG => {
423+
LowLevelILExpressionKind::RegStackFreeReg(Operation::new(function, op, index))
424+
}
421425

422426
LLIL_CALL_OUTPUT_SSA => {
423427
LowLevelILExpressionKind::CallOutputSsa(Operation::new(function, op, index))
@@ -430,6 +434,9 @@ where
430434
}
431435

432436
LLIL_ADD => LowLevelILExpressionKind::Add(Operation::new(function, op, index)),
437+
LLIL_ADD_OVERFLOW => {
438+
LowLevelILExpressionKind::AddOverflow(Operation::new(function, op, index))
439+
}
433440
LLIL_ADC => LowLevelILExpressionKind::Adc(Operation::new(function, op, index)),
434441
LLIL_SUB => LowLevelILExpressionKind::Sub(Operation::new(function, op, index)),
435442
LLIL_SBB => LowLevelILExpressionKind::Sbb(Operation::new(function, op, index)),
@@ -478,6 +485,7 @@ where
478485
LLIL_CMP_SGT => LowLevelILExpressionKind::CmpSgt(Operation::new(function, op, index)),
479486
LLIL_CMP_UGT => LowLevelILExpressionKind::CmpUgt(Operation::new(function, op, index)),
480487

488+
LLIL_TEST_BIT => LowLevelILExpressionKind::TestBit(Operation::new(function, op, index)),
481489
LLIL_BOOL_TO_INT => {
482490
LowLevelILExpressionKind::BoolToInt(Operation::new(function, op, index))
483491
}
@@ -530,9 +538,9 @@ where
530538
LowLevelILExpressionKind::UnimplMem(Operation::new(function, op, index))
531539
}
532540

533-
// TODO TEST_BIT ADD_OVERFLOW LLIL_REG_STACK_PUSH
541+
// TODO: LLIL_REG_STACK_PUSH
534542
_ => {
535-
#[cfg(debug_assertions)]
543+
// #[cfg(debug_assertions)]
536544
log::error!(
537545
"Got unexpected operation {:?} in value expr at 0x{:x}",
538546
op.operation,
@@ -663,10 +671,11 @@ where
663671
visit!(op.right());
664672
visit!(op.carry());
665673
}
666-
Add(ref op) | Sub(ref op) | And(ref op) | Or(ref op) | Xor(ref op) | Lsl(ref op)
667-
| Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op)
668-
| MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op)
669-
| Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) | Fdiv(ref op) => {
674+
Add(ref op) | AddOverflow(ref op) | Sub(ref op) | And(ref op) | Or(ref op)
675+
| Xor(ref op) | Lsl(ref op) | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op)
676+
| Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op)
677+
| Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op)
678+
| Fdiv(ref op) | TestBit(ref op) => {
670679
visit!(op.left());
671680
visit!(op.right());
672681
}
@@ -703,8 +712,8 @@ where
703712
// Do not have any sub expressions.
704713
Pop(_) | Reg(_) | RegSsa(_) | RegPartialSsa(_) | RegSplit(_) | RegSplitSsa(_)
705714
| Const(_) | ConstPtr(_) | Flag(_) | FlagBit(_) | ExternPtr(_) | FlagCond(_)
706-
| FlagGroup(_) | Unimpl(_) | Undef(_) | RegStackPop(_) | CallOutputSsa(_)
707-
| CallStackSsa(_) | FloatConst(_) => {}
715+
| FlagGroup(_) | Unimpl(_) | Undef(_) | RegStackPop(_) | RegStackFreeReg(_)
716+
| CallOutputSsa(_) | CallStackSsa(_) | FloatConst(_) => {}
708717
}
709718

710719
VisitorAction::Sibling
@@ -753,17 +762,19 @@ where
753762
ExternPtr(ref op) => &op.op,
754763

755764
RegStackPop(ref op) => &op.op,
765+
RegStackFreeReg(ref op) => &op.op,
756766

757767
CallOutputSsa(ref op) => &op.op,
758768
CallParamSsa(ref op) => &op.op,
759769
CallStackSsa(ref op) => &op.op,
760770

761771
Adc(ref op) | Sbb(ref op) | Rlc(ref op) | Rrc(ref op) => &op.op,
762772

763-
Add(ref op) | Sub(ref op) | And(ref op) | Or(ref op) | Xor(ref op) | Lsl(ref op)
764-
| Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op)
765-
| MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op)
766-
| Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) | Fdiv(ref op) => &op.op,
773+
Add(ref op) | AddOverflow(ref op) | Sub(ref op) | And(ref op) | Or(ref op)
774+
| Xor(ref op) | Lsl(ref op) | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op)
775+
| Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op)
776+
| Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op)
777+
| Fdiv(ref op) | TestBit(ref op) => &op.op,
767778

768779
DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) => &op.op,
769780

@@ -775,7 +786,6 @@ where
775786
SeparateParamListSsa(ref op) => &op.op,
776787

777788
UnimplMem(ref op) => &op.op,
778-
//TestBit(Operation<'func, M, F, operation::TestBit>), // TODO
779789
}
780790
}
781791
}
@@ -825,19 +835,19 @@ impl LowLevelILExpressionKind<'_, Mutable, NonSSA> {
825835
ExternPtr(ref op) => op.flag_write(),
826836

827837
RegStackPop(ref op) => op.flag_write(),
838+
RegStackFreeReg(ref op) => op.flag_write(),
828839

829840
CallOutputSsa(ref op) => op.flag_write(),
830841
CallParamSsa(ref op) => op.flag_write(),
831842
CallStackSsa(ref op) => op.flag_write(),
832843

833844
Adc(ref op) | Sbb(ref op) | Rlc(ref op) | Rrc(ref op) => op.flag_write(),
834845

835-
Add(ref op) | Sub(ref op) | And(ref op) | Or(ref op) | Xor(ref op) | Lsl(ref op)
836-
| Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op) | Mul(ref op)
837-
| MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op) | Modu(ref op)
838-
| Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op) | Fdiv(ref op) => {
839-
op.flag_write()
840-
}
846+
Add(ref op) | AddOverflow(ref op) | Sub(ref op) | And(ref op) | Or(ref op)
847+
| Xor(ref op) | Lsl(ref op) | Lsr(ref op) | Asr(ref op) | Rol(ref op) | Ror(ref op)
848+
| Mul(ref op) | MulsDp(ref op) | MuluDp(ref op) | Divu(ref op) | Divs(ref op)
849+
| Modu(ref op) | Mods(ref op) | Fadd(ref op) | Fsub(ref op) | Fmul(ref op)
850+
| Fdiv(ref op) | TestBit(ref op) => op.flag_write(),
841851

842852
DivuDp(ref op) | DivsDp(ref op) | ModuDp(ref op) | ModsDp(ref op) => op.flag_write(),
843853

@@ -849,7 +859,6 @@ impl LowLevelILExpressionKind<'_, Mutable, NonSSA> {
849859
SeparateParamListSsa(ref op) => op.flag_write(),
850860

851861
UnimplMem(ref op) => op.flag_write(),
852-
//TestBit(Operation<'func, M, F, operation::TestBit>), // TODO
853862
}
854863
}
855864
}

‎rust/src/low_level_il/operation.rs‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -975,6 +975,41 @@ where
975975
}
976976
}
977977

978+
// LLIL_REG_STACK_FREE_REG
979+
pub struct RegStackFreeReg;
980+
981+
impl<M, F> Operation<'_, M, F, RegStackFreeReg>
982+
where
983+
M: FunctionMutability,
984+
F: FunctionForm,
985+
{
986+
pub fn size(&self) -> usize {
987+
self.op.size
988+
}
989+
990+
pub fn dest_reg(&self) -> CoreRegister {
991+
let raw_id = self.op.operands[0] as u32;
992+
self.function
993+
.arch()
994+
.register_from_id(RegisterId(raw_id))
995+
.expect("Bad register ID")
996+
}
997+
}
998+
999+
impl<M, F> Debug for Operation<'_, M, F, RegStackFreeReg>
1000+
where
1001+
M: FunctionMutability,
1002+
F: FunctionForm,
1003+
{
1004+
fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result {
1005+
f.debug_struct("RegStackFreeReg")
1006+
.field("address", &self.address())
1007+
.field("size", &self.size())
1008+
.field("dest_reg", &self.dest_reg())
1009+
.finish()
1010+
}
1011+
}
1012+
9781013
// LLIL_FLAG, LLIL_FLAG_SSA
9791014
pub struct Flag;
9801015

@@ -2222,6 +2257,7 @@ impl OperationArguments for RegSplit {}
22222257
impl OperationArguments for RegSplitSsa {}
22232258
impl OperationArguments for RegStackPush {}
22242259
impl OperationArguments for RegStackPop {}
2260+
impl OperationArguments for RegStackFreeReg {}
22252261
impl OperationArguments for Flag {}
22262262
impl OperationArguments for FlagBit {}
22272263
impl OperationArguments for Jump {}

0 commit comments

Comments
 (0)