Add decode, disassembly, IL for TLBINV, TLBINVF

Author: noone

arch/mips/arch_mips.cpp

@@ -979,6 +979,10 @@ class MipsArchitecture: public Architecture
 				return "_readTLB";
 			case MIPS_INTRIN_TLBSEARCH:
 				return "_probeTLB";
+			case MIPS_INTRIN_TLBINV:
+				return "_invalidateTLB";
+			case MIPS_INTRIN_TLBINVF:
+				return "_invalidateTLBFlush";
 
 			case CNMIPS_INTRIN_SYNCIOBDMA:
 				return "_synciobdma";
@@ -1043,6 +1047,8 @@ class MipsArchitecture: public Architecture
 			MIPS_INTRIN_TLBSET,
 			MIPS_INTRIN_TLBGET,
 			MIPS_INTRIN_TLBSEARCH,
+			MIPS_INTRIN_TLBINV,
+			MIPS_INTRIN_TLBINVF,
 
 			CNMIPS_INTRIN_SYNCIOBDMA,
 			CNMIPS_INTRIN_SYNCS,
@@ -1200,6 +1206,15 @@ class MipsArchitecture: public Architecture
 				return {
 					NameAndType("match", Type::IntegerType(8, false)),
 				};
+			case MIPS_INTRIN_TLBINV:
+				return {
+					NameAndType("index", Type::IntegerType(8, false)),
+					NameAndType("match", Type::IntegerType(8, false)),
+				};
+			case MIPS_INTRIN_TLBINVF:
+				return {
+					NameAndType("index", Type::IntegerType(8, false)),
+				};
 			default:
 				return vector<NameAndType>();
 		}

arch/mips/il.cpp

@@ -1876,6 +1876,18 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
 			}));
 			break;
 
+		case MIPS_TLBINV:
+			il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINV, {
+				il.Register(registerSize, REG_INDEX),
+				il.Register(registerSize, REG_ENTRY_HI)
+			}));
+			break;
+
+		case MIPS_TLBINVF:
+			il.AddInstruction(il.Intrinsic({}, MIPS_INTRIN_TLBINVF, {
+				il.Register(registerSize, REG_INDEX),
+			}));
+			break;
 
 		case CNMIPS_BADDU:
 			il.AddInstruction(SetRegisterOrNop(il, 8, registerSize, op1.reg,

arch/mips/il.h

@@ -68,6 +68,8 @@ enum MipsIntrinsic : uint32_t
 		MIPS_INTRIN_TLBSET,
 		MIPS_INTRIN_TLBGET,
 		MIPS_INTRIN_TLBSEARCH,
+		MIPS_INTRIN_TLBINV,
+		MIPS_INTRIN_TLBINVF,
 
 		CNMIPS_INTRIN_SYNCIOBDMA,
 		CNMIPS_INTRIN_SYNCS,

arch/mips/mips/mips.c

@@ -743,6 +743,8 @@ static const char* const OperationStrings[] = {
 		"tgei",
 		"tgeiu",
 		"tgeu",
+		"tlbinv",
+		"tlbinvf",
 		"tlbp",
 		"tlbr",
 		"tlbwi",
@@ -1400,13 +1402,15 @@ uint32_t mips_decompose_instruction(
 				{
 					switch (ins.r.function)
 					{
-						case 1:  instruction->operation = MIPS_TLBR;  break;
-						case 2:  instruction->operation = MIPS_TLBWI; break;
- 						case 6:  instruction->operation = MIPS_TLBWR; break;
- 						case 8:  instruction->operation = MIPS_TLBP;  break;
- 						case 24: instruction->operation = MIPS_ERET;  break;
- 						case 31: instruction->operation = MIPS_DERET; break;
- 						case 32: instruction->operation = MIPS_WAIT;  break;
+						case 1:  instruction->operation = MIPS_TLBR;    break;
+						case 2:  instruction->operation = MIPS_TLBWI;   break;
+						case 3:  instruction->operation = MIPS_TLBINV;  break;
+						case 4:  instruction->operation = MIPS_TLBINVF; break;
+						case 6:  instruction->operation = MIPS_TLBWR;   break;
+						case 8:  instruction->operation = MIPS_TLBP;    break;
+						case 24: instruction->operation = MIPS_ERET;    break;
+						case 31: instruction->operation = MIPS_DERET;   break;
+						case 32: instruction->operation = MIPS_WAIT;    break;
 					}
 				}
 				break;
@@ -1674,6 +1678,8 @@ uint32_t mips_decompose_instruction(
 		case MIPS_TLBWI:
 		case MIPS_TLBR:
 		case MIPS_TLBP:
+		case MIPS_TLBINV:
+		case MIPS_TLBINVF:
 			if (((ins.value >> 6) & 0x7ff) != 0 || ins.bits.bit25 != 1)
 				return 1;
 			break;

arch/mips/mips/mips.h

@@ -451,6 +451,8 @@ namespace mips
 		MIPS_TGEI,
 		MIPS_TGEIU,
 		MIPS_TGEU,
+		MIPS_TLBINV,
+		MIPS_TLBINVF,
 		MIPS_TLBP,
 		MIPS_TLBR,
 		MIPS_TLBWI,