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Fix many of the warnings that show up when compiling with GCC 15.2
1 parent ba13f6e commit ed0f3b1

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29 files changed

+176
-179
lines changed

29 files changed

+176
-179
lines changed

‎arch/arm64/disassembler/decode_scratchpad.c‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1086,9 +1086,12 @@ static const char* const reg_lookup_c[16] = {"c0", "c1", "c2", "c3", "c4", "c5",
10861086
i++;
10871087

10881088
#define ADD_OPERAND_FLOAT32(VALUE) \
1089-
instr->operands[i].operandClass = FIMM32; \
1090-
*(float*)&(instr->operands[i].immediate) = VALUE; \
1091-
i++;
1089+
do { \
1090+
float value = VALUE; \
1091+
instr->operands[i].operandClass = FIMM32; \
1092+
memcpy(&instr->operands[i].immediate, &value, sizeof(float)); \
1093+
i++; \
1094+
} while (0)
10921095

10931096
#define ADD_OPERAND_CONST ADD_OPERAND_IMM64(const_, 0)
10941097
#define ADD_OPERAND_FBITS ADD_OPERAND_IMM32(fbits, 0)

‎arch/arm64/disassembler/format.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -383,7 +383,8 @@ uint32_t get_shifted_immediate(const InstructionOperand *instructionOperand, cha
383383
}
384384
if (type == FIMM32)
385385
{
386-
float f = *(const float*)&instructionOperand->immediate;
386+
float f = 0.0f;
387+
memcpy(&f, &instructionOperand->immediate, sizeof(float));
387388
if (snprintf(outBuffer, outBufferSize, "#%.08f%s", f, shiftBuff) >= outBufferSize)
388389
return FAILED_TO_DISASSEMBLE_OPERAND;
389390
}

‎arch/arm64/disassembler/pcode.c‎

Lines changed: 15 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -584,37 +584,29 @@ uint64_t Replicate(uint64_t val, uint8_t times, uint64_t width)
584584
https://github.com/Siguza/iometa/blob/master/src/a64.c */
585585
uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
586586
{
587-
uint64_t imm64;
588587
switch ((cmode >> 1) & 0b111)
589588
{
590589
case 0b000:
591-
imm64 = Replicate(imm8, 2, 32);
592-
break;
590+
return Replicate(imm8, 2, 32);
593591
case 0b001:
594-
imm64 = Replicate(imm8 << 8, 2, 32);
595-
break;
592+
return Replicate(imm8 << 8, 2, 32);
596593
case 0b010:
597-
imm64 = Replicate(imm8 << 16, 2, 32);
598-
break;
594+
return Replicate(imm8 << 16, 2, 32);
599595
case 0b011:
600-
imm64 = Replicate(imm8 << 24, 2, 32);
601-
break;
596+
return Replicate(imm8 << 24, 2, 32);
602597
case 0b100:
603-
imm64 = Replicate(imm8, 4, 16);
604-
break;
598+
return Replicate(imm8, 4, 16);
605599
case 0b101:
606-
imm64 = Replicate(imm8 << 8, 4, 16);
607-
break;
600+
return Replicate(imm8 << 8, 4, 16);
608601
case 0b110:
609-
imm64 = Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
610-
break;
602+
return Replicate(imm8 << (8 << (cmode & 0b1)), 2, 32);
611603
case 0b111:
612604
switch (((cmode & 0b1) << 1) | op)
613605
{
614606
case 0b00:
615-
imm64 = Replicate(imm8, 8, 8);
616-
break;
607+
return Replicate(imm8, 8, 8);
617608
case 0b01:
609+
{
618610
#if 0
619611
imm8a = Replicate((imm8 >> 7) & 0b1, 8, 1);
620612
imm8b = Replicate((imm8 >> 6) & 0b1, 8, 1);
@@ -626,26 +618,24 @@ uint64_t AdvSIMDExpandImm(uint8_t op, uint8_t cmode, uint64_t imm8)
626618
imm8h = Replicate((imm8 ) & 0b1, 8, 1);
627619
imm64 = (imm8a << 0x38) | (imm8b << 0x30) | (imm8c << 0x28) | (imm8d << 0x20) | (imm8e << 0x18) | (imm8f << 0x10) | (imm8g << 0x08) | imm8h;
628620
#else
629-
imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
621+
uint64_t imm64 = imm8 | (imm8 << (0x08 - 1)) | (imm8 << (0x10 - 2)) | (imm8 << (0x18 - 3)) |
630622
(imm8 << (0x20 - 4)) | (imm8 << (0x28 - 5)) | (imm8 << (0x30 - 6)) |
631623
(imm8 << (0x38 - 7));
632624
imm64 &= 0x0101010101010101;
633-
imm64 = Replicate(imm64, 8, 1);
625+
return Replicate(imm64, 8, 1);
634626
#endif
635-
break;
627+
}
636628
case 0b10:
637-
imm64 = Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
629+
return Replicate((((imm8 & 0xc0) ^ 0x80) << 24) |
638630
(Replicate((imm8 >> 6) & 0b1, 5, 1) << 25) | ((imm8 & 0x3f) << 19),
639631
2, 32);
640-
break;
641632
case 0b11:
642-
imm64 = (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
633+
return (((imm8 & 0xc0) ^ 0x80) << 56) | (Replicate((imm8 >> 6) & 0b1, 8, 1) << 54) |
643634
((imm8 & 0x3f) << 48);
644-
break;
645635
}
646636
break;
647637
}
648-
return imm64;
638+
return 0;
649639
}
650640

651641
bool BTypeCompatible_BTI(uint8_t hintcode, uint8_t pstate_btype)

‎arch/arm64/il.cpp‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -174,9 +174,9 @@ static ExprId GetFloat(LowLevelILFunction& il, InstructionOperand& operand, int
174174
case 2:
175175
return il.FloatConstRaw(2, operand.immediate);
176176
case 4:
177-
return il.FloatConstSingle(*(float*)&(operand.immediate));
177+
return il.FloatConstSingle(std::bit_cast<float>(static_cast<uint32_t>(operand.immediate)));
178178
case 8:
179-
return il.FloatConstDouble(*(float*)&(operand.immediate));
179+
return il.FloatConstDouble(std::bit_cast<double>(operand.immediate));
180180
default:
181181
break;
182182
}
@@ -851,7 +851,7 @@ static void LoadStoreVector(
851851
for (int i = 0; i < regs_n; ++i)
852852
{
853853
int reg_spec_base = (oper0.reg[0] + i - REG_V0) * (16 / arrspec_size) + lane;
854-
Register reg;
854+
Register reg = REG_NONE;
855855
switch (arrspec_size)
856856
{
857857
case 1:
@@ -1343,7 +1343,7 @@ bool GetLowLevelILForInstruction(
13431343
case ENC_ADD_Z_ZZ_:
13441344
if (!preferIntrinsics())
13451345
il.AddInstruction(il.Unimplemented());
1346-
return true;
1346+
return true;
13471347
default: break;
13481348
}
13491349
case ARM64_ADDS:
@@ -1372,7 +1372,7 @@ bool GetLowLevelILForInstruction(
13721372
case ENC_ANDS_P_P_PP_Z:
13731373
if (!preferIntrinsics())
13741374
il.AddInstruction(il.Unimplemented());
1375-
return true;
1375+
return true;
13761376
default: break;
13771377
}
13781378
il.AddInstruction(
@@ -1387,7 +1387,7 @@ bool GetLowLevelILForInstruction(
13871387
case ENC_ADR_Z_AZ_D_U32_SCALED:
13881388
if (!preferIntrinsics())
13891389
il.AddInstruction(il.Unimplemented());
1390-
return true;
1390+
return true;
13911391
default: break;
13921392
}
13931393
case ARM64_ADRP:
@@ -1403,7 +1403,7 @@ bool GetLowLevelILForInstruction(
14031403
case ENC_ASR_Z_ZW_:
14041404
if (!preferIntrinsics())
14051405
il.AddInstruction(il.Unimplemented());
1406-
return true;
1406+
return true;
14071407
default: break;
14081408
}
14091409
il.AddInstruction(ILSETREG_O(operand1, il.ArithShiftRight(REGSZ_O(operand2), ILREG_O(operand2),
@@ -1415,7 +1415,7 @@ bool GetLowLevelILForInstruction(
14151415
case ENC_AESD_Z_ZZ_:
14161416
if (!preferIntrinsics())
14171417
il.AddInstruction(il.Unimplemented());
1418-
return true;
1418+
return true;
14191419
default: break;
14201420
}
14211421
il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESD,
@@ -1427,8 +1427,8 @@ bool GetLowLevelILForInstruction(
14271427
case ENC_AESE_Z_ZZ_:
14281428
if (!preferIntrinsics())
14291429
il.AddInstruction(il.Unimplemented());
1430-
return true;
1431-
default: break;
1430+
return true;
1431+
default: break;
14321432
}
14331433
il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESE,
14341434
{ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1439,8 +1439,8 @@ bool GetLowLevelILForInstruction(
14391439
case ENC_AESIMC_Z_Z_:
14401440
if (!preferIntrinsics())
14411441
il.AddInstruction(il.Unimplemented());
1442-
return true;
1443-
default: break;
1442+
return true;
1443+
default: break;
14441444
}
14451445
il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESIMC,
14461446
{ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1451,8 +1451,8 @@ bool GetLowLevelILForInstruction(
14511451
case ENC_AESMC_Z_Z_:
14521452
if (!preferIntrinsics())
14531453
il.AddInstruction(il.Unimplemented());
1454-
return true;
1455-
default: break;
1454+
return true;
1455+
default: break;
14561456
}
14571457
il.AddInstruction(il.Intrinsic({RegisterOrFlag::Register(REG_O(operand1))}, ARM64_INTRIN_AESMC,
14581458
{ILREG_O(operand1), ILREG_O(operand2)}));
@@ -1571,7 +1571,7 @@ bool GetLowLevelILForInstruction(
15711571
case ENC_BICS_P_P_PP_Z:
15721572
if (!preferIntrinsics())
15731573
il.AddInstruction(il.Unimplemented());
1574-
return true;
1574+
return true;
15751575
case ENC_BIC_ASIMDIMM_L_HL:
15761576
case ENC_BIC_ASIMDIMM_L_SL:
15771577
il.AddInstruction(ILSETREG_O(operand1,
@@ -2962,9 +2962,9 @@ bool GetLowLevelILForInstruction(
29622962
case ENC_NEG_ASIMDMISC_R:
29632963
case ENC_NEG_Z_P_Z_M:
29642964
case ENC_NEG_Z_P_Z_Z:
2965-
if (!preferIntrinsics())
2966-
il.AddInstruction(il.Unimplemented());
2967-
return true;
2965+
if (!preferIntrinsics())
2966+
il.AddInstruction(il.Unimplemented());
2967+
return true;
29682968
default: break;
29692969
}
29702970
case ARM64_NEGS:
@@ -3098,8 +3098,8 @@ bool GetLowLevelILForInstruction(
30983098
{
30993099
case ENC_ORN_Z_ZI__ORR_Z_ZI_:
31003100
case ENC_ORN_P_P_PP_Z:
3101-
if (!preferIntrinsics())
3102-
il.AddInstruction(il.Unimplemented());
3101+
if (!preferIntrinsics())
3102+
il.AddInstruction(il.Unimplemented());
31033103
return true;
31043104
default: break;
31053105
}
@@ -3588,11 +3588,11 @@ bool GetLowLevelILForInstruction(
35883588
case ARM64_STR:
35893589
switch (instr.encoding)
35903590
{
3591-
case ENC_STR_P_BI_:
3592-
case ENC_STR_Z_BI_:
3593-
case ENC_STR_ZA_RI_:
3594-
if (!preferIntrinsics())
3595-
il.AddInstruction(il.Unimplemented());
3591+
case ENC_STR_P_BI_:
3592+
case ENC_STR_Z_BI_:
3593+
case ENC_STR_ZA_RI_:
3594+
if (!preferIntrinsics())
3595+
il.AddInstruction(il.Unimplemented());
35963596
return true;
35973597
default: break;
35983598
}
@@ -3619,9 +3619,9 @@ bool GetLowLevelILForInstruction(
36193619
case ENC_SUB_Z_P_ZZ_:
36203620
case ENC_SUB_Z_ZI_:
36213621
case ENC_SUB_Z_ZZ_:
3622-
if (!preferIntrinsics())
3623-
il.AddInstruction(il.Unimplemented());
3624-
return true;
3622+
if (!preferIntrinsics())
3623+
il.AddInstruction(il.Unimplemented());
3624+
return true;
36253625
default: break;
36263626
}
36273627
case ARM64_SUBS:

‎arch/armv7/CMakeLists.txt‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,3 +43,10 @@ if(BN_INTERNAL_BUILD)
4343
LIBRARY_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR}
4444
RUNTIME_OUTPUT_DIRECTORY ${BN_CORE_PLUGIN_DIR})
4545
endif()
46+
47+
if(CMAKE_CXX_COMPILER_ID MATCHES "GNU")
48+
target_compile_options(arch_armv7 PRIVATE
49+
$<$<COMPILE_LANGUAGE:CXX>:-Wno-deprecated-enum-enum-conversion>
50+
)
51+
endif()
52+

‎arch/armv7/il.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -906,7 +906,7 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI
906906
}
907907
if (op1.flags.wb)
908908
{
909-
ExprId wb;
909+
ExprId wb = BN_INVALID_OPERAND;
910910
switch (instr.operation)
911911
{
912912
case ARMV7_LDM:

‎arch/mips/arch_mips.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -811,6 +811,7 @@ class MipsArchitecture: public Architecture
811811
if (operation_name == NULL)
812812
return false;
813813
strncpy(operation, operation_name, sizeof(operation));
814+
operation[sizeof(operation) - 1] = '\0';
814815

815816
if (instr.operands[0].operandClass == V_DEST)
816817
{
@@ -3574,7 +3575,7 @@ class MipsElfRelocationHandler: public RelocationHandler
35743575
break;
35753576
default:
35763577
result[i].type = UnhandledRelocation;
3577-
LogWarn("Unsupported relocation type: %llu (%s) @0x%llX", result[i].nativeType,
3578+
LogWarn("Unsupported relocation type: %" PRIu64 " (%s) @0x%" PRIx64, result[i].nativeType,
35783579
GetRelocationString((ElfMipsRelocationType)result[i].nativeType), result[i].address);
35793580
}
35803581
}

‎arch/mips/il.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3176,7 +3176,7 @@ bool GetLowLevelILForInstruction(Architecture* arch, uint64_t addr, LowLevelILFu
31763176
case MIPS_LDC2:
31773177
case MIPS_LDC3:
31783178
{
3179-
unsigned cop;
3179+
unsigned cop = 0;
31803180
switch (instr.operation)
31813181
{
31823182
case MIPS_LDC1: cop = 1; break;

‎arch/mips/mips/mips.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3580,6 +3580,7 @@ uint32_t mips_disassemble(
35803580
const char* reg = NULL;
35813581

35823582
strncpy(operation, OperationStrings[instruction->operation], sizeof(operation));
3583+
operation[sizeof(operation) - 1] = '\0';
35833584
if (instruction->operands[0].operandClass == V_DEST)
35843585
{
35853586
char* p = dest;
@@ -3744,7 +3745,7 @@ uint32_t mips_decompose(
37443745
const uint32_t* instructionValue,
37453746
size_t size,
37463747
Instruction* restrict instruction,
3747-
uint32_t version,
3748+
MipsVersion version,
37483749
uint64_t address,
37493750
uint32_t endianBig,
37503751
uint32_t flags)

‎arch/mips/mips/test.c‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -110,11 +110,11 @@ int main(int ac, char **av)
110110
baseaddr = 0;
111111
if (0 == disassemble(insword, baseaddr, version, flags, instxt))
112112
{
113-
printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
113+
printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
114114
}
115115
else
116116
{
117-
printf("%08llX: %08X ??\n", baseaddr, insword);
117+
printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
118118
}
119119
// disassemble(0x14E00003, 0, version, flags, instxt);
120120
if (version < MIPS_32)
@@ -124,11 +124,11 @@ int main(int ac, char **av)
124124
baseaddr = 0x405a58;
125125
if (0 == disassemble(insword, baseaddr, version, flags, instxt))
126126
{
127-
printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
127+
printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
128128
}
129129
else
130130
{
131-
printf("%08llX: %08X ??\n", baseaddr, insword);
131+
printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
132132
}
133133
// disassemble(0x14E00003, 4, version, flags, instxt);
134134
if (version < MIPS_32)
@@ -186,11 +186,11 @@ int main(int ac, char **av)
186186
#endif
187187
if (0 == disassemble(insword, baseaddr, version, flags, instxt))
188188
{
189-
printf("%08llX: %08X %s\n", baseaddr, insword, instxt);
189+
printf("%08" PRIX64 ": %08X %s\n", baseaddr, insword, instxt);
190190
}
191191
else
192192
{
193-
printf("%08llX: %08X ??\n", baseaddr, insword);
193+
printf("%08" PRIX64 ": %08X ??\n", baseaddr, insword);
194194
}
195195
baseaddr += 4;
196196
p += 8;
@@ -202,3 +202,4 @@ int main(int ac, char **av)
202202
cleanup:
203203
return result;
204204
}
205+

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