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Force uniform workspace in module inputs
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modules/build/src/main/scala/scala/build/input/InputsComposer.scala

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,16 +40,16 @@ final case class InputsComposer(
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def getModuleInputs: Either[BuildException, Seq[ModuleInputs]] =
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if allowForbiddenFeatures then
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findModuleConfig match {
43-
case Right(Some(path)) =>
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val configText = os.read(path)
43+
case Right(Some(moduleConfigPath)) =>
44+
val configText = os.read(moduleConfigPath)
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for {
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table <-
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toml.Toml.parse(configText).left.map(e =>
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ModuleConfigurationError(e._2)
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) // TODO use the Address value returned to show better errors
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modules <- readAllModules(table.values.get(Keys.modules))
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_ <- checkForCycles(modules)
52-
moduleInputs <- fromModuleDefinitions(modules)
52+
moduleInputs <- fromModuleDefinitions(modules, moduleConfigPath)
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} yield moduleInputs
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case Right(None) => basicInputs
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case Left(err) => Left(err)
@@ -177,7 +177,7 @@ final case class InputsComposer(
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* @return
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* a list of module inputs for the extracted modules
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*/
180-
private def fromModuleDefinitions(modules: Seq[ModuleDefinition])
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private def fromModuleDefinitions(modules: Seq[ModuleDefinition], moduleConfigPath: os.Path)
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: Either[BuildException, Seq[ModuleInputs]] = either {
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val moduleInputsInfo = modules.map(m => m -> value(inputsFromArgs(m.roots)))
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@@ -188,6 +188,7 @@ final case class InputsComposer(
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val moduleDeps: Seq[ProjectName] = moduleDef.dependsOn.map(projectNameMap)
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inputs.dependsOn(moduleDeps)
191+
inputs.withForcedWorkspace(moduleConfigPath / os.up)
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}
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moduleInputs

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