Skip to content

Commit bd1be8a

Browse files
davemgreendavemgreen
authored
[CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (llvm#131526)
From llvm#106446, this adds a variant of getVectorIdxTy that returns an LLT. Many uses only look at the width, so a getVectorIdxWidth was added as the common base.
1 parent e614e84 commit bd1be8a

File tree

11 files changed

+40
-26
lines changed

11 files changed

+40
-26
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1375,10 +1375,9 @@ class MachineIRBuilder {
13751375
MachineInstrBuilder buildExtractVectorElementConstant(const DstOp &Res,
13761376
const SrcOp &Val,
13771377
const int Idx) {
1378-
auto TLI = getMF().getSubtarget().getTargetLowering();
1379-
unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits();
1380-
return buildExtractVectorElement(
1381-
Res, Val, buildConstant(LLT::scalar(VecIdxWidth), Idx));
1378+
const TargetLowering *TLI = getMF().getSubtarget().getTargetLowering();
1379+
LLT IdxTy = TLI->getVectorIdxLLT(getDataLayout());
1380+
return buildExtractVectorElement(Res, Val, buildConstant(IdxTy, Idx));
13821381
}
13831382

13841383
/// Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

Lines changed: 16 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -416,11 +416,25 @@ class TargetLoweringBase {
416416
return ShiftValueTy;
417417
}
418418

419+
/// Returns the type to be used for the index operand vector operations. By
420+
/// default we assume it will have the same size as an address space 0
421+
/// pointer.
422+
virtual unsigned getVectorIdxWidth(const DataLayout &DL) const {
423+
return DL.getPointerSizeInBits(0);
424+
}
425+
419426
/// Returns the type to be used for the index operand of:
420427
/// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
421428
/// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
422-
virtual MVT getVectorIdxTy(const DataLayout &DL) const {
423-
return getPointerTy(DL);
429+
MVT getVectorIdxTy(const DataLayout &DL) const {
430+
return MVT::getIntegerVT(getVectorIdxWidth(DL));
431+
}
432+
433+
/// Returns the type to be used for the index operand of:
434+
/// G_INSERT_VECTOR_ELT, G_EXTRACT_VECTOR_ELT,
435+
/// G_INSERT_SUBVECTOR, and G_EXTRACT_SUBVECTOR
436+
LLT getVectorIdxLLT(const DataLayout &DL) const {
437+
return LLT::scalar(getVectorIdxWidth(DL));
424438
}
425439

426440
/// Returns the type to be used for the EVL/AVL operand of VP nodes:

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3174,7 +3174,7 @@ bool IRTranslator::translateInsertElement(const User &U,
31743174
Register Res = getOrCreateVReg(U);
31753175
Register Val = getOrCreateVReg(*U.getOperand(0));
31763176
Register Elt = getOrCreateVReg(*U.getOperand(1));
3177-
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3177+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
31783178
Register Idx;
31793179
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
31803180
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3200,7 +3200,7 @@ bool IRTranslator::translateInsertVector(const User &U,
32003200
Register Elt = getOrCreateVReg(*U.getOperand(1));
32013201

32023202
ConstantInt *CI = cast<ConstantInt>(U.getOperand(2));
3203-
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3203+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
32043204

32053205
// Resize Index to preferred index width.
32063206
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3255,7 +3255,7 @@ bool IRTranslator::translateExtractElement(const User &U,
32553255

32563256
Register Res = getOrCreateVReg(U);
32573257
Register Val = getOrCreateVReg(*U.getOperand(0));
3258-
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3258+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
32593259
Register Idx;
32603260
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
32613261
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3279,7 +3279,7 @@ bool IRTranslator::translateExtractVector(const User &U,
32793279
Register Res = getOrCreateVReg(U);
32803280
Register Vec = getOrCreateVReg(*U.getOperand(0));
32813281
ConstantInt *CI = cast<ConstantInt>(U.getOperand(1));
3282-
unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
3282+
unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
32833283

32843284
// Resize Index to preferred index width.
32853285
if (CI->getBitWidth() != PreferredVecIdxWidth) {

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4229,7 +4229,7 @@ LegalizerHelper::scalarizeVectorBooleanStore(GStore &StoreMI) {
42294229
unsigned NumBits = MemTy.getSizeInBits();
42304230
LLT IntTy = LLT::scalar(NumBits);
42314231
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
4232-
LLT IdxTy = getLLTForMVT(TLI.getVectorIdxTy(MF.getDataLayout()));
4232+
LLT IdxTy = TLI.getVectorIdxLLT(MF.getDataLayout());
42334233

42344234
for (unsigned I = 0, E = MemTy.getNumElements(); I < E; ++I) {
42354235
auto Elt = MIRBuilder.buildExtractVectorElement(
@@ -6277,7 +6277,7 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
62776277
auto NeutralElement = getNeutralElementForVecReduce(
62786278
MI.getOpcode(), MIRBuilder, MoreTy.getElementType());
62796279

6280-
LLT IdxTy(TLI.getVectorIdxTy(MIRBuilder.getDataLayout()));
6280+
LLT IdxTy(TLI.getVectorIdxLLT(MIRBuilder.getDataLayout()));
62816281
for (size_t i = OrigTy.getNumElements(), e = MoreTy.getNumElements();
62826282
i != e; i++) {
62836283
auto Idx = MIRBuilder.buildConstant(IdxTy, i);

‎llvm/lib/CodeGen/MachineVerifier.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1993,8 +1993,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
19931993
}
19941994

19951995
auto TLI = MF->getSubtarget().getTargetLowering();
1996-
if (IdxTy.getSizeInBits() !=
1997-
TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1996+
if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
19981997
report("Index type must match VectorIdxTy", MI);
19991998
break;
20001999
}
@@ -2023,8 +2022,7 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
20232022
}
20242023

20252024
auto TLI = MF->getSubtarget().getTargetLowering();
2026-
if (IdxTy.getSizeInBits() !=
2027-
TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
2025+
if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
20282026
report("Index type must match VectorIdxTy", MI);
20292027
break;
20302028
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7549,7 +7549,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
75497549
N1VT.getVectorMinNumElements()) &&
75507550
"Extract subvector overflow!");
75517551
assert(N2C->getAPIntValue().getBitWidth() ==
7552-
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
7552+
TLI->getVectorIdxWidth(getDataLayout()) &&
75537553
"Constant index for EXTRACT_SUBVECTOR has an invalid size");
75547554

75557555
// Trivial extraction.
@@ -7783,7 +7783,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
77837783
VT.getVectorMinNumElements()) &&
77847784
"Insert subvector overflow!");
77857785
assert(N3->getAsAPIntVal().getBitWidth() ==
7786-
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
7786+
TLI->getVectorIdxWidth(getDataLayout()) &&
77877787
"Constant index for INSERT_SUBVECTOR has an invalid size");
77887788

77897789
// Trivial insertion.

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -616,6 +616,11 @@ class AArch64TargetLowering : public TargetLowering {
616616
}
617617
}
618618

619+
unsigned getVectorIdxWidth(const DataLayout &DL) const override {
620+
// The VectorIdx type is i64, with both normal and ilp32.
621+
return 64;
622+
}
623+
619624
bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
620625
const APInt &DemandedElts,
621626
TargetLoweringOpt &TLO) const override;

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -796,8 +796,8 @@ EVT AMDGPUTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
796796
return EVT::getIntegerVT(Context, 32 * ((Size + 31) / 32));
797797
}
798798

799-
MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
800-
return MVT::i32;
799+
unsigned AMDGPUTargetLowering::getVectorIdxWidth(const DataLayout &) const {
800+
return 32;
801801
}
802802

803803
bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,7 @@ class AMDGPUTargetLowering : public TargetLowering {
209209
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
210210
ISD::NodeType ExtendKind) const override;
211211

212-
MVT getVectorIdxTy(const DataLayout &) const override;
212+
unsigned getVectorIdxWidth(const DataLayout &) const override;
213213
bool isSelectSupported(SelectSupportKind) const override;
214214

215215
bool isFPImmLegal(const APFloat &Imm, EVT VT,

‎llvm/lib/Target/SPIRV/SPIRVISelLowering.h‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -43,9 +43,7 @@ class SPIRVTargetLowering : public TargetLowering {
4343

4444
// This is to prevent sexts of non-i64 vector indices which are generated
4545
// within general IRTranslator hence type generation for it is omitted.
46-
MVT getVectorIdxTy(const DataLayout &DL) const override {
47-
return MVT::getIntegerVT(32);
48-
}
46+
unsigned getVectorIdxWidth(const DataLayout &DL) const override { return 32; }
4947
unsigned getNumRegistersForCallingConv(LLVMContext &Context,
5048
CallingConv::ID CC,
5149
EVT VT) const override;

0 commit comments

Comments
 (0)