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reduced number of warnings
1 parent dea4a0d commit acd8e1c

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2 files changed

+13
-15
lines changed

2 files changed

+13
-15
lines changed

fifo.v

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,9 @@ module fifo #
2525
)
2626
(
2727
input wire clk,
28-
//input wire enable,
28+
// input wire enable,
2929
input wire clear,
30-
output wire fifo_ready,
30+
// output wire fifo_ready,
3131
input wire push,
3232
input wire pop,
3333
input wire [DATA_WIDTH - 1:0] in_data,
@@ -60,7 +60,7 @@ module fifo #
6060
if (clear == 1'b1)
6161
begin
6262
fifo_state = INITIAL_STATE;
63-
for(counter = 0; counter < FIFO_SIZE; counter = counter + 1)
63+
for(counter = 0; counter < FIFO_SIZE; counter = counter + 16'h01)
6464
fifo_data[counter] <= 0;
6565
position <= 0;
6666
data_count <= 0;
@@ -111,8 +111,8 @@ module fifo #
111111
if (data_count < FIFO_SIZE)
112112
begin
113113
fifo_data[position] <= in_data;
114-
position <= position + 1; // position is an index of next item ...
115-
data_count <= data_count + 1;
114+
position <= position + 16'h01; // position is an index of next item ...
115+
data_count <= data_count + 16'h01;
116116
fifo_state <= PUSH_FINISHED;
117117
popped_last_value <= 1'b0;
118118
if (position == FIFO_SIZE - 1)
@@ -137,12 +137,12 @@ module fifo #
137137
if (data_count > 0)
138138
begin
139139
buffer <= fifo_data[0];
140-
data_count <= data_count - 1;
140+
data_count <= data_count - 16'h01;
141141
pushed_last_value <= 0;
142-
for(counter = 0; counter < FIFO_SIZE - 1; counter = counter + 1)
142+
for(counter = 0; counter < FIFO_SIZE - 1; counter = counter + 16'h01)
143143
fifo_data[counter] <= fifo_data[counter + 1];
144144
fifo_data[FIFO_SIZE - 1] <= 0;
145-
position <= position - 1;
145+
position <= position - 16'h01;
146146
fifo_state <= POP_FINISHED;
147147
pushed_last_value <= 1'b0;
148148
if(position == 1)

quick_rs232.v

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,7 @@ module quick_rs232 #(
5959
input wire [DEFAULT_BYTE_LEN-1:0] tx_data, // data that should be send trough RS232
6060
input wire tx_data_ready, // required: setting to 1 when new data is ready to send
6161
output reg tx_data_copied, // short pulse means that data was copied _--_____--______--___
62-
output reg tx_busy, // tx notes that data is sending via RS232 or RS232 module awaiting flow-control synch
63-
output reg [7:0] debug_led_bus
62+
output reg tx_busy // tx notes that data is sending via RS232 or RS232 module awaiting flow-control synch
6463
);
6564

6665
localparam reg [3:0] IDLE_EXCHANGE_STATE = 1;
@@ -90,7 +89,7 @@ reg tx_data_parity;
9089
reg [DEFAULT_BYTE_LEN-1:0] rx_buffer;
9190
wire rx_data_buffer_full;
9291
reg [31:0] rx_bit_counter;
93-
reg [31:0] rx_stop_bit_counter_limit;
92+
// reg [31:0] rx_stop_bit_counter_limit;
9493
reg [31:0] rx_timeout;
9594
reg [3:0] rx_data_bit_counter;
9695
reg rx_data_parity;
@@ -117,7 +116,7 @@ begin
117116
rx_byte_received <= 1'b0;
118117
rx_buffer <= 0;
119118
rx_bit_counter <= 0;
120-
rx_stop_bit_counter_limit <= 0;
119+
// rx_stop_bit_counter_limit <= 0;
121120
rx_data_bit_counter <= 0;
122121
rx_data_parity <= 1'b0;
123122
rx_err <= 1'b0;
@@ -126,7 +125,6 @@ begin
126125
j <= 0;
127126
TOTAL_RX_TIMEOUT <= 6400; // ~ 9600 bit/s
128127
rx_timeout <= 0;
129-
debug_led_bus <= 8'b11111111;
130128
end
131129
else
132130
begin
@@ -213,7 +211,7 @@ begin
213211
if (rx_bit_counter == TICKS_PER_UART_BIT)
214212
begin
215213
rx_bit_counter <= 0;
216-
rx_data_bit_counter <= rx_data_bit_counter + 1;
214+
rx_data_bit_counter <= rx_data_bit_counter + 4'b0001;
217215
end
218216
end
219217
end
@@ -419,7 +417,7 @@ begin
419417
if (tx_bit_counter == TICKS_PER_UART_BIT)
420418
begin
421419
tx_bit_counter <= 0;
422-
tx_data_bit_counter <= tx_data_bit_counter + 1;
420+
tx_data_bit_counter <= tx_data_bit_counter + 4'b0001;
423421
end
424422
end
425423
end

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