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Commit 965fb5e

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author
Mario Ruiz
committed
First design that builds
1 parent 844b0c0 commit 965fb5e

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3 files changed

+57
-13
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3 files changed

+57
-13
lines changed

‎examples/07_udp/benchmark_kernel.tcl‎

Lines changed: 42 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ if {[llength ${bd_design}] == 0} {
5151
save_bd_design
5252

5353
# Network Layer Box
54-
proc modify_hier_nlb { nlb_index} {
54+
proc modify_hier_nlb { nlb_index } {
5555

5656
variable script_folder
5757

@@ -67,11 +67,12 @@ proc modify_hier_nlb { nlb_index} {
6767
set hier_obj [get_bd_cell $nameHier]
6868
current_bd_instance $hier_obj
6969

70+
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 summary
71+
7072
for {set idx 0} {$idx < 4} {incr idx} {
7173
create_bd_cell -type ip -vlnv xilinx.com:RTLKernel:traffic_generator:1.0 traffic_generator_${idx}
7274
}
7375

74-
create_bd_cell -type ip -vlnv xilinx.com:hls:collector:1.0 collector_0
7576
create_bd_cell -type ip -vlnv xilinx.com:RTLKernel:switch_wrapper:1.0 switch_wrapper_0
7677

7778
for {set idx 0} {$idx < 4} {incr idx} {
@@ -82,12 +83,12 @@ proc modify_hier_nlb { nlb_index} {
8283
connect_bd_intf_net [get_bd_intf_pins switch_wrapper_0/m_tx_out] [get_bd_intf_pins networklayer/S_AXIS_sk2nl]
8384
connect_bd_intf_net [get_bd_intf_pins networklayer/M_AXIS_nl2sk] [get_bd_intf_pins switch_wrapper_0/s_rx_in]
8485

85-
connect_bd_intf_net [get_bd_intf_pins traffic_generator_0/M_AXIS_summary] [get_bd_intf_pins collector_0/summary]
86+
connect_bd_intf_net [get_bd_intf_pins traffic_generator_0/M_AXIS_summary] [get_bd_intf_pins summary]
8687

8788
save_bd_design
8889

8990
set_property -dict [list \
90-
CONFIG.NUM_MI {6} \
91+
CONFIG.NUM_MI {5} \
9192
] [get_bd_cells smartconnect]
9293

9394
for {set idx 0} {$idx < 4} {incr idx} {
@@ -97,12 +98,8 @@ proc modify_hier_nlb { nlb_index} {
9798
connect_bd_intf_net [get_bd_intf_pins smartconnect/M0${port}_AXI] [get_bd_intf_pins traffic_generator_${idx}/S_AXIL]
9899
}
99100

100-
connect_bd_intf_net [get_bd_intf_pins smartconnect/M05_AXI] [get_bd_intf_pins collector_0/s_axi_control]
101-
102101
save_bd_design
103102

104-
connect_bd_net [get_bd_pins ap_clk] [get_bd_pins collector_0/ap_clk]
105-
connect_bd_net [get_bd_pins ap_rst_n] [get_bd_pins collector_0/ap_rst_n]
106103
connect_bd_net [get_bd_pins ap_clk] [get_bd_pins switch_wrapper_0/ap_clk]
107104
connect_bd_net [get_bd_pins ap_rst_n] [get_bd_pins switch_wrapper_0/ap_rst_n]
108105

@@ -116,33 +113,67 @@ proc modify_hier_nlb { nlb_index} {
116113
}
117114
}
118115

116+
save_bd_design
117+
# Restore current instance
118+
current_bd_instance $oldCurInst
119+
}
120+
121+
# Modify Base Logic
122+
proc modify_base_logic { nlb_index } {
123+
124+
variable script_folder
125+
126+
# Save current instance; Restore later
127+
set oldCurInst [current_bd_instance .]
128+
129+
# Set parent object as current
130+
set parentObj [current_bd_instance .]
131+
current_bd_instance $parentObj
132+
133+
# Get bd cell and set as current instance
134+
set nameHier "base_logic"
135+
set hier_obj [get_bd_cell $nameHier]
136+
current_bd_instance $hier_obj
137+
138+
save_bd_design
139+
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "summary_${nlb_index}"
140+
save_bd_design
141+
connect_bd_intf_net [get_bd_intf_pins summary_${nlb_index}] [get_bd_intf_pins collector_${nlb_index}/summary]
142+
save_bd_design
143+
119144
foreach pcie_noc {CPM_PCIE_NOC_0 CPM_PCIE_NOC_1} {
120145
set offset_increment [expr 0x1000000 * ${nlb_index} + 2048]
121-
assign_bd_address -offset [expr {0x020104002000 + ${offset_increment}}] -range 512 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs collector_0/s_axi_control/Reg] -force
146+
#delete_bd_objs [get_bd_addr_segs cips/${pcie_noc}/SEG_collector_${nlb_index}_Reg]
147+
assign_bd_address -offset [expr {0x020104002000 + ${offset_increment}}] -range 512 -target_address_space [get_bd_addr_spaces cips/${pcie_noc}] [get_bd_addr_segs collector_${nlb_index}/s_axi_control/Reg] -force
122148
save_bd_design
123149
}
124150

125-
save_bd_design
126151
# Restore current instance
127152
current_bd_instance $oldCurInst
153+
connect_bd_intf_net [get_bd_intf_pins nlb${nlb_index}/summary] [get_bd_intf_pins base_logic/summary_${nlb_index}]
154+
save_bd_design
128155
}
129156

130157
# Create network hierarchy
131158
if { ${DCMAC0_ENABLED} == "1" } {
132159
modify_hier_nlb 0
160+
modify_base_logic 0
133161
if { ${DUAL_QSFP_DCMAC0} == "1"} {
134162
modify_hier_nlb 1
163+
modify_base_logic 0
135164
}
136165
save_bd_design
137166
}
138167
if { ${DCMAC1_ENABLED} == "1" } {
139168
modify_hier_nlb 2
169+
modify_base_logic 2
140170
if { ${DUAL_QSFP_DCMAC1} == "1"} {
141171
modify_hier_nlb 3
172+
modify_base_logic 3
142173
}
143174
save_bd_design
144175
}
145176

146177
save_bd_design
147178

148-
#close_bd_design [get_bd_designs top]
179+
#close_bd_design [get_bd_designs top]

‎examples/07_udp/network_layer.tcl‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,15 +42,28 @@ update_ip_catalog
4242
open_bd_design {${exec_dir}/build/prj.srcs/sources_1/bd/top/top.bd}
4343
save_bd_design
4444

45+
if { ${DCMAC0_ENABLED} == "1" || ${DCMAC1_ENABLED} == "1"} {
46+
set_property CONFIG.NUM_CLKS {2} [get_bd_cells bar_sc]
47+
connect_bd_net [get_bd_pins bar_sc/aclk1] [get_bd_pins base_logic/clk_out2]
48+
}
49+
4550
# Create network hierarchy
4651
if { ${DCMAC0_ENABLED} == "1" } {
52+
disconnect_bd_net /clock_reset_resetn_pl_ic [get_bd_pins qsfp_0_n_1/ap_rst_n]
53+
disconnect_bd_net /cips_pl0_ref_clk [get_bd_pins qsfp_0_n_1/ap_clk]
54+
connect_bd_net [get_bd_pins base_logic/clk_out2] [get_bd_pins qsfp_0_n_1/ap_clk]
55+
connect_bd_net [get_bd_pins base_logic/peripheral_aresetn] [get_bd_pins qsfp_0_n_1/ap_rst_n]
4756
create_network_layer_box 0
4857
if { ${DUAL_QSFP_DCMAC0} == "1"} {
4958
create_network_layer_box 1
5059
}
5160
save_bd_design
5261
}
5362
if { ${DCMAC1_ENABLED} == "1" } {
63+
disconnect_bd_net /clock_reset_resetn_pl_ic [get_bd_pins qsfp_2_n_3/ap_rst_n]
64+
disconnect_bd_net /cips_pl0_ref_clk [get_bd_pins qsfp_2_n_3/ap_clk]
65+
connect_bd_net [get_bd_pins base_logic/clk_out2] [get_bd_pins qsfp_2_n_3/ap_clk]
66+
connect_bd_net [get_bd_pins base_logic/peripheral_aresetn] [get_bd_pins qsfp_2_n_3/ap_rst_n]
5467
create_network_layer_box 2
5568
if { ${DUAL_QSFP_DCMAC1} == "1"} {
5669
create_network_layer_box 3

‎submodules/v80-vitis-flow/resources/dcmac/tcl/nlb.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,8 +178,8 @@ proc create_network_layer_box { nlb_index } {
178178
connect_bd_intf_net [get_bd_intf_pins ${qsfp_hier_name}/M_AXIS_${qsfp_interface}] [get_bd_intf_pins ${nlb_hier_name}/RX_AXIS]
179179
connect_bd_intf_net [get_bd_intf_pins ${qsfp_hier_name}/S_AXIS_${qsfp_interface}] [get_bd_intf_pins ${nlb_hier_name}/TX_AXIS]
180180

181-
connect_bd_net [get_bd_pins cips/pl0_ref_clk] [get_bd_pins ${nlb_hier_name}/ap_clk]
182-
connect_bd_net [get_bd_pins clock_reset/resetn_pl_ic] [get_bd_pins ${nlb_hier_name}/ap_rst_n]
181+
connect_bd_net [get_bd_pins base_logic/clk_out2] [get_bd_pins ${nlb_hier_name}/ap_clk]
182+
connect_bd_net [get_bd_pins base_logic/peripheral_aresetn] [get_bd_pins ${nlb_hier_name}/ap_rst_n]
183183
save_bd_design
184184

185185
set offset_increment [expr 0x1000000 * ${nlb_index}]

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