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New Tutorial: AIE/D/15-farrow_filter
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‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/Makefile‎

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#
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# Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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#
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# Author: Faisal El-Shabani
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ECHO = @echo
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export TARGET ?= hw_emu
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export AIE_SIM_ONLY := false
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# Platform Selection...
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VERSAL_VITIS_PLATFORM = xilinx_vck190_base_202320_1
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VITIS_PLATFORM_DIR = ${PLATFORM_REPO_PATHS}/${VERSAL_VITIS_PLATFORM}
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export VITIS_PLATFORM_XPFM = ${VITIS_PLATFORM_DIR}/${VERSAL_VITIS_PLATFORM}.xpfm
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# Set SysRoot, RootFS and Image
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export VITIS_SYSROOTS = ${COMMON_IMAGE_VERSAL}/sysroots/cortexa72-cortexa53-xilinx-linux
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export SDKTARGETSYSROOT = ${VITIS_SYSROOTS}
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export KERNEL_IMAGE = ${COMMON_IMAGE_VERSAL}/Image
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export ROOTFS = ${COMMON_IMAGE_VERSAL}/rootfs.ext4
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export XLNX_VERSAL = ${COMMON_IMAGE_VERSAL}
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export PLATFORM = ${VITIS_PLATFORM_XPFM}
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export SYSROOT = ${SDKTARGETSYSROOT}
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##############
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# Build Flow #
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##############
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.PHONY: clean help gen_vectors
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help::
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$(ECHO) "Makefile Usage:"
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$(ECHO) " make all"
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$(ECHO) " Command to generate everything for this design"
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$(ECHO) ""
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$(ECHO) " make clean"
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$(ECHO) " Command to remove all the generated files."
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gen_vectors:
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matlab -batch "gen_vectors"
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all: farrow_design
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farrow_design:
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$(MAKE) compile -C aie/farrow_final
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$(MAKE) all -C hls/farrow_dma_snk
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$(MAKE) all -C hls/farrow_dma_src
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$(MAKE) all -C ps_apps/hw_emu
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$(MAKE) all -C vitis
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clean:
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$(MAKE) clean -C aie/farrow_final
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$(MAKE) clean -C hls/farrow_dma_snk
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$(MAKE) clean -C hls/farrow_dma_src
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$(MAKE) clean -C ps_apps/hw_emu
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$(MAKE) clean -C vitis
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@/bin/rm -rf .crashReporter*

‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/README.md‎

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‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/aie/farrow_final/Makefile‎

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#
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# Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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# SPDX-License-Identifier: MIT
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#
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# Author: Faisal El-Shabani
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AIE_SIM_ONLY ?= true
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PLATFORM_USE := xilinx_vck190_base_202320_1
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PLATFORM := ${PLATFORM_REPO_PATHS}/${PLATFORM_USE}/${PLATFORM_USE}.xpfm
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MY_APP = farrow_app.cpp
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MY_SOURCES = ${MY_APP} farrow_graph.h farrow_kernel1.cpp farrow_kernel1.h farrow_kernel2.cpp farrow_kernel2.h
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LOG_FILE = log
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OTHER_OPTS = --aie.pl-freq=625.0 --aie.Xchess="-std=c++17"
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ALL_INCLUDE := --include=${PWD}
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AIE_FLAGS := --aie.verbose ${ALL_INCLUDE} ${MY_APP} ${OTHER_OPTS} --platform=${PLATFORM} --aie.Xmapper=BufferOptLevel9 --aie.xlopt=1
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ifeq (${AIE_SIM_ONLY},true)
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AIE_FLAGS := ${AIE_FLAGS} --aie.Xpreproc="-DAIE_SIM_ONLY"
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endif
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.PHONY: clean help compile sim
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help::
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@echo "Makefile Usage:"
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@echo " make all"
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@echo " Command to generate everything for this design"
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@echo ""
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@echo " make compile"
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@echo " Run AIE compiler and build the design"
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@echo ""
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@echo " make sim"
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@echo " Run AIE simulator"
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@echo ""
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@echo " make clean"
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@echo " Command to remove all the generated files."
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all : compile sim get_II check_sim_output_aie
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x86all : x86compile x86sim check_sim_output_x86
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compile: ${MY_SOURCES}
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v++ -c --mode aie --target=hw ${AIE_FLAGS} 2>&1 | tee ${LOG_FILE}
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x86compile:
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v++ -c --mode aie --target=x86sim ${AIE_FLAGS} 2>&1 | tee ${LOG_FILE}
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sim:
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aiesimulator --profile --online -wdb -text -i=../.. 2>&1 | tee -a ${LOG_FILE}
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x86sim:
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x86simulator 2>&1 -i=../.. | tee -a ${LOG_FILE}
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check_sim_output_aie:
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matlab -batch "check_sim_output('hw')"
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check_sim_output_x86:
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matlab -batch "check_sim_output('x86sim')"
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throughput:
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@../../scripts/throughput.py aiesimulator_output/data/sig_o.txt --iscomplex
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get_II:
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@../../scripts/get_loop_II.py Work/aie/
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clean:
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@rm -rf Work* .Xil function_wdb_dir .crashReporter .AIE_SIM_CMD_LINE_OPTIONS AIECompiler.log xcd.log log aiesimulator_output x86simulator_output diff_output pl_sample_count* tmp vitis_analyzer.* xsc_report.log diag_report.log libadf.a sol.db t.txt Map_Report.csv AIESimulator.log
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@rm -rf ISS_RPC_SERVER_PORT system_flat.wcfg system.wcfg system.wdb tmp.vcd.vcd trdata.aiesim vcdanalyze.log vitis_analyzer_pid* logs VCDAnalyze.log

‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/aie/farrow_final/check_sim_output.m‎

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%
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% Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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% SPDX-License-Identifier: MIT
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%
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% Author: Faisal El-Shabani
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function check_sim_output(TARGET)
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%% Read golden output
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fileID = fopen('../../data/sig_o.txt','r');
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formatSpec = '%f %f %f %f';
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[sig_g] = fscanf(fileID,formatSpec).';
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fclose(fileID);
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sig_g = [complex(sig_g(1:4:end),sig_g(2:4:end));complex(sig_g(3:4:end),sig_g(4:4:end))];
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sig_g = sig_g(:).';
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if (TARGET=="hw")
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fileID = fopen('aiesimulator_output/data/sig_o.txt','r');
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txt = textscan(fileID,'%s','delimiter','\n');
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fclose(fileID);
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txt{1}(strcmp(txt{1},'TLAST'))=[];
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tmp = zeros(1,size(txt{1},1));
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for i=2:2:size(txt{1},1)
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x = strsplit(txt{1}{i},' ');
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tmp(i-1) = complex(str2double(x{1}),str2double(x{2}));
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tmp(i) = complex(str2double(x{3}),str2double(x{4}));
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end
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sig_o_sim = tmp;
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y1 = strsplit(txt{1}{1},' ');
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if strcmp(y1(end),'ns') factor = 1; elseif strcmp(y1(end),'us') factor = 1000; elseif strcmp(y1(end),'ps') factor = 1/1000; end
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y1 = str2num(y1{2})*factor;
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y2 = strsplit(txt{1}{end-1},' ');
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if strcmp(y2(end),'ns') factor = 1; elseif strcmp(y2(end),'us') factor = 1000; elseif strcmp(y2(end),'ps') factor = 1/1000; end
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y2 = str2num(y2{2})*factor;
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throughput = round(size(sig_o_sim,2)/(y2-y1)*1000,1);
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fprintf('Raw Throughput = %.1f MSPS\n',throughput);
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elseif (TARGET=="x86sim")
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fileID = fopen('x86simulator_output/data/sig_o.txt','r');
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formatSpec = '%f %f %f %f';
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[sig_o_sim] = fscanf(fileID,formatSpec).';
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fclose(fileID);
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sig_o_sim = [complex(sig_o_sim(1:4:end),sig_o_sim(2:4:end));complex(sig_o_sim(3:4:end),sig_o_sim(4:4:end))];
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sig_o_sim = sig_o_sim(:).';
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end
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fprintf('Max error LSB = %d\n',max(max(real(sig_g-sig_o_sim)),max(imag(sig_g-sig_o_sim))));
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end

‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/aie/farrow_final/farrow_app.cpp‎

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//
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// Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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// SPDX-License-Identifier: MIT
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//
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// Author: Faisal El-Shabani
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#include "farrow_graph.h"
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using namespace adf;
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class dut_graph : public graph {
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farrow_graph farrow;
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public:
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std::array< input_plio,1> sig_i;
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std::array< input_plio,1> del_i;
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std::array<output_plio,1> sig_o;
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dut_graph( void )
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{
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#ifdef AIE_SIM_ONLY
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sig_i[0] = input_plio::create("PLIO_i_0",plio_64_bits,"data/sig_i.txt");
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del_i[0] = input_plio::create("PLIO_i_1",plio_64_bits,"data/del_i_optimized.txt");
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sig_o[0] = output_plio::create("PLIO_o_0",plio_64_bits,"data/sig_o.txt");
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#else
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sig_i[0] = input_plio::create("PLIO_i_0",plio_64_bits);
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del_i[0] = input_plio::create("PLIO_i_1",plio_64_bits);
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sig_o[0] = output_plio::create("PLIO_o_0",plio_64_bits);
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#endif
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connect<stream>(sig_i[0].out[0],farrow.sig_i[0]);
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connect<stream>(del_i[0].out[0],farrow.del_i[0]);
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connect<stream>(farrow.sig_o[0],sig_o[0].in[0]);
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}
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};
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// Instantiate AIE graph:
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dut_graph aie_dut;
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// Initialize and run the graph:
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int main(void)
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{
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aie_dut.init();
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aie_dut.run(4);
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aie_dut.end();
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return 0;
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}

‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/aie/farrow_final/farrow_graph.h‎

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//
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// Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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// SPDX-License-Identifier: MIT
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//
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// Author: Faisal El-Shabani
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#pragma once
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#include <adf.h>
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#include "farrow_kernel1.h"
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#include "farrow_kernel2.h"
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using namespace adf;
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// ------------------------------------------------------------
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// Top Level Graph
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// ------------------------------------------------------------
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class farrow_graph : public graph {
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public:
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// Declare Kernels
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kernel farrow_kernel1_ins;
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kernel farrow_kernel2_ins;
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std::array<port<input>,1> sig_i;
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std::array<port<input>,1> del_i;
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std::array<port<output>,1> sig_o;
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farrow_graph( void )
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{
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farrow_kernel1_ins = kernel::create_object<farrow_kernel1>();
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source(farrow_kernel1_ins) = "farrow_kernel1.cpp";
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runtime<ratio>(farrow_kernel1_ins) = 0.9;
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farrow_kernel2_ins = kernel::create_object<farrow_kernel2>();
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source(farrow_kernel2_ins) = "farrow_kernel2.cpp";
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runtime<ratio>(farrow_kernel2_ins) = 0.9;
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location<stack>(farrow_kernel1_ins) = location<kernel>(farrow_kernel1_ins);
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location<stack>(farrow_kernel2_ins) = location<kernel>(farrow_kernel2_ins);
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// Connect inputs:
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connect<> ( sig_i[0], farrow_kernel1_ins.in[0] );
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connect<> ( del_i[0], farrow_kernel2_ins.in[0] );
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connect<> ( farrow_kernel1_ins.out[0], farrow_kernel2_ins.in[1] );
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connect<> ( farrow_kernel1_ins.out[1], farrow_kernel2_ins.in[2] );
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connect<> ( farrow_kernel1_ins.out[2], farrow_kernel2_ins.in[3] );
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connect<> ( farrow_kernel1_ins.out[3], farrow_kernel2_ins.in[4] );
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// Connect outputs:
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connect<>( farrow_kernel2_ins.out[0], sig_o[0] );
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}
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};
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‎AI_Engine_Development/AIE/Design_Tutorials/15-farrow_filter/aie/farrow_final/farrow_kernel1.cpp‎

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//
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// Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
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// SPDX-License-Identifier: MIT
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//
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// Author: Faisal El-Shabani
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#include <adf.h>
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#include <aie_api/aie.hpp>
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#include "farrow_kernel1.h"
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#include <aie_api/utils.hpp>
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// ------------------------------------------------------------
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// Constructor
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// ------------------------------------------------------------
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farrow_kernel1::farrow_kernel1( void )
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{
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aie::set_rounding(aie::rounding_mode::symmetric_inf);
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aie::set_saturation(aie::saturation_mode::saturate);
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for(int i=0;i<STATE_LEN;i++)
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{
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f_state[i] = (cint16){0,0};
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}
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}
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// ------------------------------------------------------------
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// Run
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// ------------------------------------------------------------
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void farrow_kernel1::run( input_buffer<TT_SIG,adf::extents<BUFFER_SIZE>>& __restrict sig_i,
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output_buffer<TT_SIG,adf::extents<BUFFER_SIZE>>& __restrict y3,
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output_buffer<TT_SIG,adf::extents<BUFFER_SIZE>>& __restrict y2,
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output_buffer<TT_SIG,adf::extents<BUFFER_SIZE>>& __restrict y1,
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output_buffer<TT_SIG,adf::extents<BUFFER_SIZE>>& __restrict y0)
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{
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aie::accum<TT_ACC,8> acc_f3;
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aie::accum<TT_ACC,8> acc_f2;
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aie::accum<TT_ACC,8> acc_f1;
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aie::accum<TT_ACC,8> acc_f0;
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aie::vector<cint16,16> v_buff;
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v_buff.insert(1,aie::load_v<8>( f_state ) );
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aie::vector<int16,16> f_coeffs = aie::load_v<16>(f_taps);
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auto p_sig_i = aie::begin_vector<8>(sig_i);
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auto p_y3 = aie::begin_vector<8>(y3);
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auto p_y2 = aie::begin_vector<8>(y2);
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auto p_y1 = aie::begin_vector<8>(y1);
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auto p_y0 = aie::begin_vector<8>(y0);
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// Loop over some samples:
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for ( unsigned rr=0; rr < BUFFER_SIZE/16; rr++)
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chess_loop_range(1,0)
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chess_prepare_for_pipelining
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{
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v_buff.insert(0,*p_sig_i++);
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acc_f3 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_antisym(f_coeffs,0,v_buff,9);
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*p_y3++ = acc_f3.to_vector<TT_SIG>(DNSHIFT);
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acc_f2 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_sym(f_coeffs,4,v_buff,9);
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*p_y2++ = acc_f2.to_vector<TT_SIG>(DNSHIFT);
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acc_f1 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_antisym(f_coeffs,8,v_buff,9);
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*p_y1++ = acc_f1.to_vector<TT_SIG>(DNSHIFT);
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acc_f0 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_sym(f_coeffs,12,v_buff,9);
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*p_y0++ = acc_f0.to_vector<TT_SIG>(DNSHIFT);
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v_buff.insert(1,*p_sig_i++);
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acc_f3 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_antisym(f_coeffs,0,v_buff,1);
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*p_y3++ = acc_f3.to_vector<TT_SIG>(DNSHIFT);
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acc_f2 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_sym(f_coeffs,4,v_buff,1);
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*p_y2++ = acc_f2.to_vector<TT_SIG>(DNSHIFT);
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acc_f1 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_antisym(f_coeffs,8,v_buff,1);
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*p_y1++ = acc_f1.to_vector<TT_SIG>(DNSHIFT);
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acc_f0 = aie::sliding_mul_sym_xy_ops<8,8,1,1,int16,cint16>::mul_sym(f_coeffs,12,v_buff,1);
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*p_y0++ = acc_f0.to_vector<TT_SIG>(DNSHIFT);
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}
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*(v8cint16*)f_state = v_buff.extract<8>(1);
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}

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